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| Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Document order number: MC33742 Rev 2.0, 10/2004 Advance Information System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver The 33742 and the 33742S are monolithic integrated circuits combining many functions frequently used by automotive environmental control units (ECUs). The 33742 is an SBC having a fully protected fixed 5.0 V low-drop regulator with current limit, overtemperature pre-warning, and reset. An output drive with sense input is also provided to implement a second 5.0 V regulator, using an external PNP bipolar junction transistor. The 33742 has normal, standby, stop, and sleep modes, an internally switched high-side power supply output with four wake-up inputs, programmable window watchdog, interrupt, reset, SPI input control, and a high-speed CAN transceiver compatible with CAN 2.0 A and B protocols for module-to-module communication. Features * High-Speed 1.0 Mbps CAN Interface with Bus Diagnostic Capability (Detection of CANH and CANL Short to Ground, to VDD, and to VSUP) * Low-Drop Voltage 5.0 V, 200 mA VDD Regulator with Current-Limiting, Overtemperature Pre-Warning, and Output Monitoring with Reset * Additional 5.0 V Regulator with External Series Pass Transistor * Normal, Standby, Stop, and Sleep Modes with Low Sleep and Stop Mode Current * 150 mA High-Side Switch Output for Control of External Circuitry * Four External Wake-Up Inputs * Software-Programmable Watchdog Window, Interrupt, and Reset 33742 33742S SYSTEM BASIS CHIP WITH ENHANCED HIGH-SPEED CAN Freescale Semiconductor, Inc... DW SUFFIX CASE 751F-05 28-TERMINAL SOICW ORDERING INFORMATION Device MC33742DW/R2 MC33742SDW/R2 Temperature Range (TA) -40C to 125C Package 28 SOICW 33742 Simplified Application Diagram VPWR 33742 33742 5.0 V MCU RST VDD VSUP V2 V2CTRL V2 VPWR CS SCLK MOSI MISO SPI CS SCLK MOSI MISO INT L0 L1 L2 L3 WDOG HS CANH CANL GND Safe Circuitry ECU Local Supply Twisted Pair CAN Bus TXD RXD GND This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Motorola, Inc. 2004 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table 1. Significance Device Differences Motorola Part No. 33742 Reset Duration 15 ms (typical) Device Differences The duration of the reset mode, in which the RST terminal is asserted low, is 15 ms typical. Reset mode is entered after device power up, when a VDD undervoltage condition occurred and if the watchdog register is not properly triggered. The duration of the reset mode, in which the RST terminal is asserted low, is 3.5 ms typical. Reset mode is entered after device power up, when a VDD undervoltage condition occurred and if the watchdog register is not properly triggered. See Page 15 33742S 3.5 ms (typical) 15 Freescale Semiconductor, Inc... V2CTRL V2 VSUP VSUP Monitor CAN Dual Voltage Regulator 5.0 V/200 mA Supply VDD Monitor HS Control Mode Control Oscillator Interrupt Watchdog Reset VDD HS L0 L1 L2 L3 Programmable Wake-Up Input INT WDOG RST SPI V2 MOSI SCLK MISO CS CANH CANL High-Speed 1.0 Mbps CAN Physical Interface TXD RXD GND Figure 1. 33742 Simplified Internal Block Diagram 33742 2 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. RXD TXD VDD RST INT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 WDOG CS GND GND GND GND V2 V2CTRL VSUP HS L0 MOSI MISO SCLK GND GND GND GND CANL CANH L3 L2 L1 Freescale Semiconductor, Inc... TERMINAL DEFINITIONS A functional description of each terminal can be found in the System/Application Information section beginning on page 18. Terminal 1 2 3 4 5 6-9 20-23 10 11 12 13 14-17 Terminal Name RXD TXD VDD RST Formal Name Receive Data Transmit Data Voltage Digital Drain Reset Output (Active LOW) Interrupt Output (Active LOW) Ground Voltage Source 2 Voltage Source 2 Control Voltage Supply High-Side Output Level 0 -3 Inputs CAN bus receive data output CAN bus transmit data input 5.0 V regulator output terminal. Definition This is the device reset output whose main function is to reset the MCU. This terminal has an internal pull-up current source to VDD This output is asserted LOW when an enabled interrupt condition occurs. The output is a push-pull structure. Ground of the IC. These terminals are connected to the package lead frame in order to provide a thermal path. Sense input for V2 regulator using external ballast. V2 is also the internal supply for the CAN cell. Output driver for the external ballast transistor. Supply input for the complete device. Output of internal high-side switch. Current capability is internally limited to 150 mA. Input interfaces to external circuitry (switched or ICs). Levels at these terminals can be read by SPI and input can be used as programmable wake-up input in Sleep or Stop mode. CAN high output. CAN low output. Clock input for the Serial Peripheral Interface (SPI) of the device. SPI data sent to MCU. When CS is HIGH, terminal is high impedance. SPI data received by the 33742. Chip select terminal for SPI. When CS is LOW, device is selected. Output of watchdog circuitry. Terminal is asserted LOW if software watchdog is not correctly triggered. INT GND V2 V2CTRL VSUP HS L0-L3 18 19 24 25 26 27 28 CANH CANL SCLK MISO MOSI CS CAN High CAN Low Serial Data Clock Master In/Slave Out Master Out/Slave In Chip Select (Active LOW) Watchdog Output (Active LOW) WDOG MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33742 3 Freescale Semiconductor, Inc. MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Rating Symbol Value Unit ELECTRICAL RATINGS Power Supply Voltage at VSUP Terminal Continuous (Steady-State) Transient Voltage (Load Dump) Logic Inputs (RXD, TXD, MOSI, MISO, CS, SCLK, RST, WDOG, and INT Terminals) Output Current at VDD Terminal HS Terminal VLOG IDD VHS IHS VESD1 4000 2000 VESD2 VDCIN IDCIN VTRINEC PD VCANH/L ICANH/L VLDH/L VTRH/L 200 V VSUP -0.3 to 27 -0.3 to 40 -0.3 to VDD + 0.3 Internally Limited V A V Freescale Semiconductor, Inc... Voltage Output Current ESD Voltage, Human Body Model (Note 1) HS, L0, L1, L2, L3, CANH, CANL Terminals All Other Terminals ESD Voltage, Machine Model (Note 2) L0, L1, L2, L3 Terminals DC Input Voltage DC Input Current Transient Input Voltage with External Component (Note 3) Power Dissipation (Note 4) CANL and CANH Terminals Continuous Voltage Continuous Current CANH and CANL Transient Voltage (Load Dump) (Note 5) CANH and CANL Transient Voltage (Note 6) -0.3 to VSUP + 0.3 Internally Limited V A V -0.3 to 40 2.0 100 1.0 -27 to 40 200 40 40 V mA V W V mA V V Notes 1. ESD1 testing is performed in accordance with the Human Body Model (CZAP =100 pF, RZAP =1500 ). 2. 3. 4. 5. 6. ESD2 testing is performed in accordance with the Machine Model (CZAP =200 pF, RZAP =0 ). Testing in accordance with ISO 7637-1. See also Figure 2. Maximum power dissipation at 85C ambient temperature in free air with no heatsink, according to JEDEC JESD51-2 and JESD51-3 specifications. Load dump test in accordance with ISO 7637-1. Transient test in accordance with ISO 7637-1. See also Figure 3. 33742 1.0 nF Lx 10 k GND Transient Pulse Generator (Note) GND 33742 1.0 nF CANH CANL GND 1.0 nF Transient Pulse Generator (Note) GND Note Waveform per ISO 7637-1. Test Pulses 1, 2, 3a, and 3b. Note Waveform per ISO 7637-1. Test Pulses 1, 2, 3a, and 3b. Figure 2. ISO 7637 Test Setup for L0:L3 Inputs Figure 3. ISO 7637 Test Setup for CANH/CANL 33742 4 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. MAXIMUM RATINGS (continued) All voltages are with respect to ground unless otherwise noted. Rating Symbol Value Unit THERMAL RATINGS Operating Temperature Ambient Junction Storage Temperature Thermal Resistance Junction to GND Terminals Peak Package Reflow Temperature During Solder Mounting (Note 7) TA TJ TSTG RJG T SOLDER -40 to 125 -40 to 150 -55 to 165 20 240 C C/W C C Freescale Semiconductor, Inc... Notes 7. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33742 5 Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.75 V V2 5.25 V, 5.5 V VSUP 18 V, and -40C TA 125C. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit VSUP TERMINAL Nominal DC Supply Voltage Extended DC Voltage Full Functionality (Note 8) Reduced Functionality (Note 9) Input Voltage During Load Dump Input Voltage During Jump Start VSUP-LD VSUP-JS ISUP(STDBY) - - ISUP(NORM) - - ISUP(SLP-WD) - - - ISUP(SLP-WE) - - - ISUP(STOP-WD) - - - - 80 100 160 160 210 80 65 55 - - - A 85 53 110 105 80 140 A 12.4 15 15 19 A 12 14.5 15 19 mA VSUP VSUP-EX 18 4.5 - - - - - - 27 5.5 40 27 V V mA 5.5 - 18 V V Freescale Semiconductor, Inc... Supply Current in Standby Mode (Note 10) (IOUT at VDD = 10 mA, CAN Recessive or Sleep Mode) TA 25C TA = -40C to 25C Supply Current in Normal Mode (Note 10) (IOUT at VDD = 10 mA, CAN Recessive or Sleep Mode) TA 25C TA = -40C to 25C Supply Current in Sleep Mode (Note 10) [VDD and V2 OFF, CAN in Sleep Mode with CAN Wake-Up Disabled (Note 11)] VSUP < 13.5 V, Oscillator Running (Note 12) VSUP < 13.5 V, Oscillator Not Running (Note 13) VSUP = 18 V, Oscillator Running (Note 12) Supply Current in Sleep Mode (Note 10) [VDD and V2 OFF, VSUP < 13.5 V, Oscillator Not Running (Note 13), CAN in Sleep Mode with Wake-Up Enabled] TA = -40C TA = 25C TA = 125C Supply Current in Stop Mode (Note 10) [IOUT at VDD < 2.0 mA, VDD ON, CAN in Sleep Mode with Wake-Up Disabled (Note 11) VSUP < 13.5 V, Oscillator Running (Note 12) VSUP < 13.5 V, Oscillator Not Running (Note 13) VSUP = 18 V, Oscillator Running (Note 12) Notes 8. All functions and modes available and operating. Watchdog, HS turn ON/turn OFF, CAN cell operating, L0:L3 inputs operating, SPI read/ write operation. Overtemperature may occur. 9. VDD > 4.0 V, RST HIGH if reset 2 selected by SPI, logic terminal high level reduced, device is functional. 10. 11. 12. 13. Current measured at VSUP terminal. If CAN cell is Sleep-Enabled for wake-up, an additional current (ICAN-SLEEP) must be added to specified value. Oscillator running means one of the following function is active: Forced Wake-Up or Cyclic Sense or Software Watchdog in Stop mode. Oscillator not running means none of the following functions are active: Forced Wake-Up and Cyclic Sense and Software Watchdog in Stop mode. 33742 6 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.75 V V2 5.25 V, 5.5 V VSUP 18 V, and -40C TA 125C. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit VSUP TERMINAL (continued) Supply Current in Stop Mode (Note 14) [IOUT at VDD < 2.0 mA, VDD ON, VSUP < 13.5 V, Oscillator Not Running (Note 15), CAN in Sleep Mode with Wake-Up Enabled] TA = -40C TA = 25C TA = 125C BATFAIL Flag Internal Threshold VBF VBF(HYS) VBF(EW) 5.3 VBF(EW-HYST) 0.1 0.2 0.3 5.8 6.3 V ISUP(STOP-WE) A - - - 1.5 - 100 92 80 3.0 1.0 - - - 4.0 - V V V Freescale Semiconductor, Inc... BATFAIL Flag Hysteresis (Note 16) Battery Fall Early Warning Threshold In Normal and Standby Modes Battery Fall Early Warning Hysteresis In Normal and Standby Modes (Note 16) VDD TERMINAL (Note 17) VDD Output Voltage (2.0 mA < IDD < 200 mA) 5.5 V < VSUP < 27 V 4.5 V < VSUP < 5.5 V Dropout Voltage IDD = 200 mA Dropout Voltage, Limited Output Current and Low VSUP IDD = 50 mA, 4.5 V < VSUP VDD Output Current Internally Limited Thermal Shutdown (Junction) Normal or Standby Mode Overtemperature Pre-Warning (Junction) VDDTEMP Bit Set Temperature Threshold Difference RST Threshold, Selectable by RSTTH Bit in SPI Register RCR VDDOUT 4.9 4.0 VDDDRP1 - VDDDRP2 - IDD 200 TSD 160 TPW 125 TSD - TPW VRSTTH 4.5 4.0 VDDR 1.0 4.6 4.2 - 4.7 4.3 VRSTTH 20 - - 160 40 - 200 285 350 0.1 0.25 0.2 0.5 5.0 - 5.1 - V V V mA C C C V Threshold 1, Default Value after Reset, RSTTH Bit set to 0 Threshold 2, RSTTH bit Set to 1 VDD for Reset Active Notes 14. Current measured at VSUP terminal. 15. 16. 17. V Oscillator not running means none of the following functions are active: Forced Wake-Up and Cyclic Sense and Software Watchdog in Stop mode. Guaranteed by design; however, it is not production tested. IDD is the total regulator output current. VDD specification with external capacitor. Stability requirement: Capacitance > 47 F, ESR < 1.3 (tantalum capacitor). In Reset, Normal Request, Normal and Standby modes. Measures with capacitance = 47 F tantalum. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33742 7 Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.75 V V2 5.25 V, 5.5 V VSUP 18 V, and -40C TA 125C. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit VDD TERMINAL (continued) (Note 18) Line Regulation (IDD = 10 mA, Capacitance = 47 F Tantalum at VDD) 9.0 V < VSUP < 18 V 5.5 V < VSUP < 27 V Load Regulation (Capacitance = 47 F Tantalum at VDD) 1.0 mA < IDD < 200 mA Thermal Stability VTHERM-S - 30 50 VLD - 25 75 mV VLR - - 5.0 10 25 25 mV mV Freescale Semiconductor, Inc... VSUP = 13.5 V, IDD = 100 mA (Note 19) VDD TERMINAL IN STOP MODE (Note 18) VDD Output Voltage IDD 2.0 mA IDD 10 mA IDD Output Current to Wake-Up Reset Threshold Selectable by SPI, Default Value after Reset, Bit Value 0 Selectable by SPI, Bit Value 1 Line Regulation (Capacitance = 47 F Tantalum at VDD) 5.5 V < VSUP < 27 V, IDD = 2.0 mA Load Regulation (Capacitance = 47 F Tantalum at VDD) 1.0 mA < IDD < 10 mA VLD-STOP - 15 75 VLR-STOP - 5.0 25 mV VDDSTOP 4.75 4.75 5.0 5.0 17 5.25 5.25 25 V IDDS-WU VRST-STOP 10 mA V 4.5 4.1 4.6 4.2 4.7 4.3 mV V2 TRACKING VOLTAGE REGULATOR (Note 20) V2 Output Voltage (Capacitance = 10 F Tantalum at V2) 2.0 mA I2 200 mA, 5.5 V < VSUP < 27 V I2 Output Current (for Information Only) Depending on External Ballast Transistor V2 Control Drive Current Capability (Note 21) Worst Case at TJ = 125C V2LOW Flag Threshold V2 0.99 1.0 1.01 VDD I2 200 - - mA I2CTRL 0 - 4.0 10 4.25 mA V2LTH 3.75 V Notes 18. IDD is the total regulator output current. VDD specification with external capacitor. Stability requirement: capacitance > 47 F, ESR < 1.3 (tantalum capacitor). In Reset, Normal Request, Normal and Standby modes, measures with capacitance = 47 F tantalum. 19. Guaranteed by characterization and design; however, it is not production tested. 20. V2 specification with external capacitor. Stability requirement: capacitance > 42 F and ESR < 1.3 (tantalum capacitor), external resistor between base and emitter required. Measurement conditions: ballast transistor MJD32C, capacitance > 10 F tantalum, 2.2 k resistor between base and emitter of ballast transistor. 21. Guaranteed current capability of the V2CTRL terminal is 10 mA. Current may be higher. No active limitation is provided. 33742 8 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.75 V V2 5.25 V, 5.5 V VSUP 18 V, and -40C TA 125C. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit LOGIC OUTPUT TERMINAL (MISO) (Note 22) Low-Level Output Voltage IOUT = 1.5 mA High-Level Output Voltage IOUT = -250 A Tri-Stated MISO Leakage Current 0 V < VMISO < VDD VOL 0 - 1.0 V VOH VDD - 0.9 - VDD V IHZ -2.0 - 2.0 A Freescale Semiconductor, Inc... LOGIC INPUT TERMINALS (MOSI, SCLK, CS) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current on CS VI = 4.0 V Low-Level Input Current on CS VI = 1.0 V MOSI and SCLK Input Current 0 V < VIN < VDD VIH VIL I IH 0.7 VDD -0.3 - - VDD + 0.3 0.3 VDD -20 V V A -100 - I IL -100 - -20 A I IN -10 - 10 A RST OUTPUT TERMINAL (Note 23) High-Level Output Current 0 V < VOUT < 0.7 VDD Low-Level Output Voltage IO = 1.5 mA, 5.5 V < VSUP < 27 V IO = 0 mA, 1.0 V IOH -300 VOL 0 0 IPDW 2.3 - 5.0 - - 0.9 0.9 -250 -150 A V mA V > 0.9 V WDOG OUTPUT TERMINAL (Note 24) Low-Level Output Voltage IO = 1.5 mA, 1.0 V < VSUP < 27 V High-Level Output Voltage IO = -250 A VOH VDD -0.9 - VDD VOL 0 - 0.9 V V INT OUTPUT TERMINAL (Note 24) Low-Level Output Voltage IO = 1.5 mA High-Level Output Voltage IO = -250 A VOH VDD -0.9 - VDD VOL 0 - 0.9 V V Notes 22. Push-pull structure with tri-state condition (CS HIGH). 23. Output terminal only. Supply from VDD. Structure switch to ground with pullup current source. 24. Push-pull structure. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33742 9 Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.75 V V2 5.25 V, 5.5 V VSUP 18 V, and -40C TA 125C. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit HS OUTPUT TERMINAL Driver Output ON Resistance TJ = 25C, IOUT - 150 mA, VSUP > 9.0 V TA = 125C, IOUT - 150 mA, VSUP > 9.0 V TA = 125C, IOUT - 120 mA, 5.5 V < VSUP < 9.0 V Output Current Limitation VSUP - VHS > 1.0 V ILIM 160 TSD ILEAK VCL -1.5 - -0.3 155 - - - - 500 190 10 C A V RDS(ON) - - - 2.0 - 3.5 2.5 4.5 5.5 mA Freescale Semiconductor, Inc... HS Thermal Shutdown HS Leakage Current Output Clamp Voltage IOUT = -10 mA, No Inductive Load Drive Capability L0, L2, L2, AND L3 INPUT TERMINALS Negative Switching Threshold 5.5 V < VSUP < 6.0 V 6.0 V < VSUP < 18 V 18 V < VSUP < 27 V Positive Switching Threshold 5.5 V < VSUP < 6.0 V 6.0 V < VSUP < 18 V 18 V < VSUP < 27 V Hysteresis 5.5 V < VSUP < 27 V Input Current -0.2 V < VIN < 40 V I IN -10 - 10 VHYST 0.6 - 1.3 A VTHP 2.7 3.0 3.5 3.3 4.0 4.2 3.8 4.6 4.7 V VTHN 2.0 2.5 2.7 2.5 3.0 3.2 3.0 3.6 3.7 V V CAN SUPPLY Supply Current of CAN Cell CAN in Normal Mode, Bus Recessive State CAN in Normal Mode, Bus Dominant State without Bus Load CAN in Sleep State, Wake-Up Enabled, V2 Regulator OFF CAN in Sleep State, Wake-Up Disabled, V2 Regulator OFF (Note 25) Notes 25. Guaranteed by design; however, it is not production tested. IRES IDOM ICAN-SLEEP IDIS - - - - 1.3 1.5 12 - 3.0 3.5 24 1.0 mA mA A A 33742 10 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.75 V V2 5.25 V, 5.5 V VSUP 18 V, and -40C TA 125C. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit CANH AND CANL TERMINALS Bus Terminals Common Mode Voltage Differential Input Voltage (Common Mode Between -3.0 V and 7.0 V) Recessive State at RXD Dominant State at RXD Differential Input Hysteresis (RXD) Input Resistance VHYST RIN RIND VCANH 2.75 - VCANL 0.5 2.0 VoH -VoL 1.5 - ICANH ICANL TSD ICANL/OC ICANH/OC ICAN1 - -60 - ICAN2 - -60 - 40 -50 190 100 - 240 3.0 -50 60 10 - 75 A - - 3.0 100 V mV mA - 35 160 - - 180 -35 - - C mA 60 -200 - - 200 -60 A - - 2.25 - - - 4.5 3.0 V VCM VCANH - VCANL - 900 100 5.0 10 - - - - - 500 - - 100 100 mV k k V -27 - 40 V mV Freescale Semiconductor, Inc... Differential Input Resistance CANH Output Voltage TXD Dominant State TXD Recessive State CANL Output Voltage TXD Dominant State TXD Recessive State Differential Output Voltage TXD Dominant State TXD Recessive State Output Current Capability (Dominant State) CANH CANL Overtemperature Shutdown CANL Overcurrent Detection (Note 26) CANL CANH CANH and CANL Input Current, Device Supplied (CAN Sleep Mode with CAN Wake-Up Enabled or Disabled) VCANH, VCANL from 0 V to 5.0 V VCANH, VCANL = -2.0 V VCANH, VCANL = 7.0 V CANH and CANL Input Current, Device Unsupplied VCANH, VCANL = 2.5 V VCANH, VCANL = -2.0 V VCANH, VCANL = 7.0 V Notes 26. Reported in CAN register. For a description of the contents of the CAN register, refer to CAN Register (CAN) on page 40. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33742 11 Freescale Semiconductor, Inc. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.75 V V2 5.25 V, 5.5 V VSUP 18 V, and -40C TA 125C. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit CANH AND CANL DIAGNOSTIC INFORMATION CANL to GND Threshold CANH to GND Threshold CANL to VSUP Threshold CANH to VSUP Threshold CANL to VDD Threshold VLG VHG VLVB VHVB VL5 VH5 IRXDW - 100 - - - - - - - 1.75 1.75 VSUP - 2.0 VSUP - 2.0 VDD - 0.43 VDD - 0.43 - - - - - - V V V V V V A Freescale Semiconductor, Inc... CANH to VDD Threshold RXD Weak Pulldown Current Source (Note 27) RXD Permanent Dominant Failure Condition TXD AND RXD TERMINALS TXD Input High Voltage TXD Input Low Voltage TXD High-Level Input Current VTXD = V2 TXD Low-Level Input Current VTXD = 0 V RXD Output High Voltage IRXD = 250 A RXD Output Low Voltage IRXD = 1.0 mA Notes 27. Guaranteed by design; however, it is not production tested. VOL - - 0.5 VOH VDD - 1.0 - - V IIL -150 -100 -50 V VIH VIL IIH -10 - 10 A 0.7 VDD -0.4 - - VDD + 0.4 0.3 VDD V V A 33742 12 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.75 V V2 5.25 V, 5.5 V VSUP 18 V, and -40C TA 125C. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit DIGITAL INTERFACE TIMING (Note 28) SPI Operation Frequency SCLK Clock Period SCLK Clock High Time SCLK Clock Low Time Falling Edge of CS to Rising Edge of SCLK f REQ t PCLK t WSCLKH t WSCLKL t LEAD t LAG t SISU t SIH t RSO 0.25 250 125 125 100 100 40 40 - - - - - - - - 4.0 N/A N/A N/A N/A N/A N/A N/A MHz ns ns ns ns ns ns ns ns Freescale Semiconductor, Inc... Falling Edge of SCLK to Rising Edge of CS MOSI to Falling Edge of SCLK Falling Edge of SCLK to MOSI MISO Rise Time (Note 29) CL = 220 pF MISO Fall Time (Note 29) CL = 220 pF Time from Falling or Rising Edges of CS MISO Low Impedance MISO High Impedance Time from Rising Edge of SCLK to MISO Data Valid 0.2 VDD MISO 0.8 VDD, CL = 200 pF - 25 50 ns t FSO - 25 50 ns t SOEN t SODIS t VALID - - - - 50 50 ns - - 50 STATE MACHINE TIMING Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command) and Stop Mode Activation (Note 30) Interrupt Low-Level Duration Stop Mode Internal Oscillator Frequency (Note 31) Watchdog Period Normal and Standby Modes Period 1 Period 2 Period 3 Period 4 Notes 28. 29. 30. 31. See Figure 4, SPI Timing Diagram, page 17. Not production tested. Guaranteed by design. Not production tested. Guaranteed by design. Detected by V2 OFF. f OSC is indirectly measured (1.0 ms reset) and trimmed. t CS-STOP 18 - 10 100 34 s s 7.0 13 - kHz ms 8.58 39.6 88 308 9.75 45 100 350 10.92 50.4 112 392 t INT f OSC t WD - MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33742 13 Freescale Semiconductor, Inc. DYNAMIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.75 V V2 5.25 V, 5.5 V VSUP 18 V, and -40C TA 125C. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit STATE MACHINE TIMING (continued) Normal Request Mode Timeout Normal Request Mode Watchdog Period Stop Mode Period 1 Period 2 Period 3 Period 4 t NRTOUT 308 350 392 ms t WD-STOP 6.82 31.5 70 245 f ACC -12 -30 - - 4.6 9.25 18.5 37 74 95.5 191 388 350 12 30 9.75 45 100 350 12.7 58.5 130 455 ms Freescale Semiconductor, Inc... Watchdog Period Accuracy Normal and Standby Modes Stop Mode Cyclic Sense/FWU Timing Sleep and Stop Modes Timing 1 Timing 2 Timing 3 Timing 4 Timing 5 Timing 6 Timing 7 Timing 8 Cyclic Sense ON Time Sleep and Stop Modes. Cyclic Sense/FWU Timing Accuracy Sleep and Stop Modes Delay Between SPI Command and HS Turn ON (Note 32) Normal or Standby Mode, VSUP > 9.0 V Delay Between SPI Command and HS Turn OFF (Note 32) Normal or Standby Mode, VSUP > 9.0 V Delay Between SPI and V2 Turn ON (Note 32) Standby Mode Delay Between SPI and V2 Turn OFF (Note 32) Normal Mode Delay Between Normal Request and Normal Mode After Watchdog Trigger Command (Note 32) Normal Request Mode Delay Between SPI and CAN Normal Mode (Note 32) Normal Mode (Note 33) Delay Between SPI and CAN Sleep Mode (Note 32) Normal Mode (Note 33) % t CSFWU 3.22 6.47 12.9 25.9 51.8 66.8 134 271 5.98 12 24 48.1 96.2 124 248 504 ms t ON 200 500 s t ACC -30 - - 30 % s 22 s 22 s 9.0 - 22 s 9.0 - 22 s 15 35 70 s - - 10 s - - 10 t S-HSON t S-HSOFF t S-V2ON t S-V2OFF t S-NR2N - - - t S-CAN_N t S-CAN_S Notes 32. Delay starts at falling edge of clock cycle #8 of the SPI command and start of "Turn ON" or "Turn OFF" of HS or V2. 33. Guaranteed by design; however, it is not production tested. 33742 14 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. DYNAMIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.75 V V2 5.25 V, 5.5 V VSUP 18 V, and -40C TA 125C. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit STATE MACHINE TIMING (continued) Delay Between CS Wake-Up (CS LOW to HIGH) and Device in Normal Request Mode (VDD ON and RST HIGH) Stop Mode Delay Between CS Wake-Up (CS LOW to HIGH) and First Accepted SPI Command Device in Stop Mode After Wake-Up Delay Between INT Pulse and First SPI Command Accepted t W-CS 15 40 90 s t W-SPI 90 - N/A s t S-1STSPI 20 - - N/A - s s Freescale Semiconductor, Inc... Device in Stop Mode After Wake-Up Delay Between Two SPI Messages Addressing the Same Register t 2SPI 25 VDD TERMINAL Reset Delay Time Measured at 50% of Reset Signal IDD Overcurrent to Wake-Up Deglitcher Time (Note 34) tD 4.0 - 55 30 75 s s tIDD-DGLT 40 RST TERMINAL Reset Duration After VDD HIGH 33742 33742S ms t RSTDUR t RSTDURS 12 3.0 15 3.5 18 4.0 L0, L2, L2, AND L3 INPUT TERMINALS Wake-Up Filter Time Notes 34. Guaranteed by design; however, it is not production tested. t WUF 8.0 20 38 s MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33742 15 Freescale Semiconductor, Inc. DYNAMIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.75 V V2 5.25 V, 5.5 V VSUP 18 V, and -40C TA 125C. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit CAN MODULE TIMING Dominant State Timeout Propagation Loop Delay TXD to RXD (Recessive to Dominant) (Note 35) Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 Propagation Delay TXD to CAN (Recessive to Dominant) (Note 36) t DOUT t LRD 200 360 520 s ns 60 70 80 110 100 110 130 200 65 80 100 160 50 210 225 255 310 ns 110 150 200 300 140 ns ns t TRD 20 25 35 50 Freescale Semiconductor, Inc... Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 Propagation Delay CAN to RXD (Recessive to Dominant) (Note 37) Propagation Loop Delay TXD to RXD (Dominant to Recessive) (Note 35) Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 Propagation Delay TXD to CAN (Dominant to Recessive) (Note 36) Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 Propagation Delay CAN to RXD (Dominant to Recessive) (Note 37) Non-Differential Slew Rate (CANL or CANH) Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 Notes 35. See Figure 5, page 17. 36. See Figure 6, page 17. 37. See Figure 7, page 17. t RRD t LDR 10 100 120 140 250 150 165 200 340 125 150 180 310 30 200 220 250 410 ns 150 190 250 460 60 ns V/s t TDR 60 65 75 200 t RDR t SL3 t SL2 t SL1 t SL0 20 4.0 3.0 2.0 1.0 19 13.5 8.0 5.0 40 20 15 10 33742 16 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. Timing Diagrams t PCLK CS t LEAD t WSCLKH t LAG SCLK t WSCLKL t SISU t SIH Freescale Semiconductor, Inc... MOSI Undefined t VALID t SOEN Di 0 Don't Care Di 8 Don't Care t SODIS MISO Do 0 Do 8 Note Incoming data at MOSI terminal is sampled by the 33742 at SCLK falling edge. Outgoing data at MISO terminal is set by the 33742 at SCLK rising edge (after t VALID delay time). Figure 4. SPI Timing Diagram tLRD TX 0.8 V 2.0 V VDIFF 0.9 V tRRD tRDR 0.5 V tLDR RX RX 0.8 V 2.0 V 0.8 V 2.0 V Figure 7. Propagation Delay CAN to RXD Figure 5. Propagation Loop Delay TXD to RXD tTRD TX 0.8 V 2.0 V tTDR VDIFF 0.9 V 0.5 V Figure 6. Propagation Delay TXD to CAN MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33742 17 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. SYSTEM/APPLICATION INFORMATION INTRODUCTION The 33742 and the 33742S are integrated circuits dedicated to automotive applications. Their functions include the following: * One fully protected voltage regulator with 200 mA total output current capability available at the VDD terminal. * Driver for external pass transistor for V2 regulator function. * VDD regulator undervoltage reset function, programmable window or timeout software watchdog function. * Two running modes: Normal and Standby modes when the microcontroller is running. * Sleep and Stop modes for operation in low power mode to reduce the application current consumption, while offering wake-up capability from CAN interface, L3:L0 wake-up input, and automatic timer wake-up. * Programmable wake-up input and cyclic sense wake-up. * CAN high-speed physical interface with bus failure diagnostic and enhanced protection feature for TXD and RXD failure. * Interface with micro through SPI. Interrupt output to report device status, diagnostic, and wake-up event. Freescale Semiconductor, Inc... FUNCTIONAL TERMINAL DESCRIPTION RXD and TXD The RXD and TXD terminals (receive data terminal and transmit data terminal, respectively) are connected to the microcontroller CAN protocol handler. TXD is an input and controls the CANH and CANL line state (dominant when TXD is LOW, recessive when TXD is HIGH). RXD is an output and reports the bus state (RXD LOW when CAN bus is dominant, HIGH when CAN bus is recessive). V2 The V2 terminal is the input sense of the V2 regulator. It is connected to the external ballast transistor. V2 is also the 5.0 V supply of the internal CAN interface. It is possible to connect V2 to an external 5.0 V regulator or to the VDD output when no external ballast transistor is used. In this case, the V2CTRL terminal must be left open. Refer to Figure 28, 33742 Typical Application Schematic, page 46. VDD The VDD terminal is the output terminal of the 5.0 V internal regulator. It can deliver up to 200 mA. This output is protected against overcurrent and overtemperature. It includes an overtemperature pre-warning flag, which is set when the internal regulator temperature exceeds 130C typical. When the temperature exceeds the overtemperature shutdown (170C typical), the regulator is turned off. VDD includes an undervoltage reset circuitry, which sets the RST terminal LOW when VDD is below the undervoltage reset threshold. V2CTRL The V2CTRL terminal is the output drive of the V2 regulator connected to the external ballast transistor. VSUP The VSUP terminal is the battery supply input of the device. HS The HS terminal is the internal high-side driver output. It is internally protected against overcurrent and overtemperature. RST The Reset terminal RST is an output that is set LOW when the device is in reset mode. The RST terminal is set HIGH when the device is not in reset mode. RST includes an internal pullup current source. When RST is LOW, the sink current capability is limited, allowing RST to be shorted to 5.0 V for software debug or software download purposes. L0, L1, L2, and L3 The L0:L3 input terminals can be connected to external switches or any IC's output. The state of the inputs can be read by SPI. Theses inputs can be used as wake-up events when the device is set in Sleep or Stop mode. CANH and CANL The CAN High and CAN Low terminals are the interfaces to the CAN bus lines. They are controlled by TXD input level, and the state of CANH and CANL is reported through RXD output. A 60 impedance termination is connected between CANH and CANL. INT The Interrupt terminal INT is an output that is set LOW when an interrupt occurs. INT is enabled using the Interrupt Register (INTR). When INT occurs, INT stays LOW until the INT source is cleared. INT output also reports a wake-up event by a 10 s typical pulse when the device is in stop mode. 33742 18 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. SCLK This is the Serial Data Clock terminal of the serial peripheral interface. MOSI This is the Master Out/Slave In terminal of the serial peripheral interface. Control data from the microcontroller are received through this terminal. MISO This is the Master In/Slave Out terminal of the serial peripheral interface. Data are send from the device to the microcontroller through MISO terminal. CS This is the device Chip Select terminal of the serial peripheral interface. When this terminal is LOW, the internal serial peripheral interface of the device is selected. WDOG The Watchdog terminal is used to signal that a software watchdog has not been properly triggered. Freescale Semiconductor, Inc... DEVICE OPERATION Power Supply The 33742 is supplied from the battery line through the VSUP terminal. An external diode is required to protect against negative transients and reverse battery. The 33742 can operate from 4.5 VDC and under jump-start conditions at 27 VDC. The VSUP terminal sustains standard automotive voltage conditions such as load dump at 40 V. When VSUP falls below 3.0 V typical, the 33742 detects it and stores the information in the Mode Control Register (MCR) bit BATFAIL. Detection is available in all operation modes. Note For a detailed description of all the registers mentioned in this section, refer to the section titled SPI INTERFACE AND REGISTER DESCRIPTION beginning on page 38. The 33742 incorporates a battery early warning function, which provides a maskable interrupt when the VSUP voltage is below 6.0 V typical. A hysteresis is included. Operation is only in Normal and Standby modes. VSUP LOW is reported in the Input/Output Register (IOR). regulator. The recommended ballast transistor is MJD32C. Other transistors can be used, however. Depending on the PNP transistor gain, an external resistor-capacitor network might be connected. V2 is the supply input for the CAN cell. The state of V2 is reported in the IOR register (bit V2LOW set to logic [1] if V2 is below 4.0 V typical). HS VSUP Switch Output HS output is a 2.0 typical switch from VSUP terminal. It allows the supply of external switches and their associated pullup or pulldown circuitry, in conjunction, for example, with the wake-up input terminals L0:L3. Output current is limited to 200 mA and HS is protected against short circuit and has an overtemperature shutdown (bit HSOT in the IOR register and bit HSOT-V2LOW in the INTR register). HS output is controlled by the bit HSON in the IOR register. Thanks to an internal timer, HS can be activated at regular intervals in Sleep and Stop modes. It can also be permanently turned on in Normal or Standby modes to drive loads or supply peripheral components. No internal clamping protection circuit is implemented; thus dedicated external protection circuitry is required in case of inductive load drive. HS negative voltage should not go below -0.3 V. VDD Regulator The VDD regulator is a 5.0 V output with output current capability up to 200 mA. It includes a voltage monitoring circuitry associated with an undervoltage reset function. The VDD regulator is fully protected against overcurrent and short circuit. It has overtemperature detection warning flags (bit VDDTEMP in the MCR and INTR registers) and overtemperature shutdown with hysteresis. Battery Fail Early Warning Refer to the discussion under the heading Power Supply, above. Internal Clock The 33742 has an internal clock used to generate all timings (reset, watchdog, cyclic wake-up, filtering time, etc.). Two oscillators are implemented. A high-accuracy (12 percent) oscillator used in Normal Request, Normal, and Standby modes, and a low-accuracy (30 percent) oscillator used in Sleep and Stop modes. V2 Regulator V2 regulator circuitry is designed to drive an external pass transistor increasing output current flexibility. Two terminals, V2 and V2CTRL, are used to achieve the flexibility. Output voltage is 5.0 V and is realized by a tracking function of the VDD MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33742 19 Freescale Semiconductor, Inc. Functional Modes The 33742 has four modes of operation, all controlled by the SPI. The modes are Standby, Normal, Stop, and Sleep. An additional temporary mode called Normal Request mode is automatically accessed by the device after reset or wake-up from Stop mode. A Reset mode is also implemented. Special modes and configuration are possible for debug and program microcontroller flash memory. Table 2 below offers a summary of the functional modes. Reset Mode In the Reset mode, the RST terminal is LOW and a timer runs for t RSTDUR time. After t RSTDUR has elapsed, the 33742 enters Normal Request mode. Reset mode is entered if a reset condition occurs (VDD LOW, watchdog timeout, or watchdog trigger in a closed window). Normal Request Mode Normal Request mode is a temporary mode automatically accessed by the 33742 after the Reset mode or after the 33742 wakes up from Stop mode. After wake-up from the Sleep mode or after device power-up, the 33742 enters the Reset mode before entering the Normal Request mode. After a wake-up from the Stop mode, the 33742 enters the Normal Request mode directly. Freescale Semiconductor, Inc... Table 2. Table of Operation Mode Voltage Regulator HS Switch VDD: ON, V2: OFF, HS: OFF VDD: ON, V2: ON, HS: Controllable VDD: ON, V2: OFF, HS: Controllable VDD: ON (Limited Current Capability), V2: OFF, HS:OFF or Cyclic Sense VDD: OFF, V2: OFF, HS: OFF or Cyclic Same as Normal Wake-Up Capabilities (if Enabled) - RST Terminal INT Terminal Watchdog Software CAN Cell Normal Request Low for t RSTDUR time, then HIGH - - - Normal - Normally HIGH. If enabled, signal Active LOW if failure (VDD WDOG or VDD Pre-Warning Temp, CAN, HS) undervoltage occurs Same as Normal mode Normally HIGH. Active LOW if WDOG (Note 40) or VDD undervoltage occurs Same as Normal mode Running TXD/RXD Standby - Running Low power Stop CAN, SPI, L0:L3, Cyclic Sense, Forced Wake-Up, IDD Overcurrent (Note 39) CAN, SPI, L0:L3, Cyclic Sense Forced Wake-Up - Signal 33742 wake-up and IDD > IDDS-WU (not maskable) Running if enabled. Not running if disabled Low power. Wake-up capability if enabled Sleep Normal Debug (Note 38) Standby Debug (Note 38) Stop Debug (Note 38) Flash Programming LOW Normally HIGH. Active LOW if VDD undervoltage occurs Normally HIGH. Active LOW if VDD undervoltage occurs Normally HIGH. Active LOW if VDD undervoltage occurs Not operating Not Active Not running Low power. Wake-up capability if enabled Same as Normal Same as Normal Not running Same as Standby - Same as Standby Not running Same as Standby Same as Stop Same as Stop Same as Stop Not running Same as Stop Forced externally - Not operating Not operating Not Operating Notes 38. Mode entered via special sequence described under the heading Debug Mode: Hardware and Software Debug with the 33742 beginning on page 25. 39. IDD overcurrent always enabled. 40. WDOG if enabled. 33742 20 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. In Normal Request mode, the VDD regulator is ON, the V2 regulator is OFF, and the RST terminal is HIGH. As soon as the 33742 enters the Normal Request mode, an internal 350 ms timer is started (parameter tNRTOUT). During these 350 ms, the MCU of the application must address the 33742 via SPI and configure the TIM1 subregister to select the watchdog period. This is the condition for the 33742 to stop the 350 ms timer and go into the Normal or Standby mode and set the watchdog timer according to the configuration. Normal Request Entered and No Watchdog Configuration Occurs If the Normal Request mode is entered after the 33742 powers up or after a wake-up from Stop mode, and if no watchdog configuration occurs while the 33742 is in Normal Request mode, the 33742 goes into Reset mode after the 350 ms time period has expired before again going into Normal Request mode. If no watchdog configuration is achieved, the 33742 alternatively goes from Normal Request mode, to Reset mode, to Normal Request mode, and so on. If the Normal Request mode is entered after a wake-up from Sleep mode, and if no watchdog configuration occurs while the 33742 is in Normal Request mode, the 33742 goes back to Sleep mode. Normal Mode In Normal mode, both the VDD and V2 regulators are ON. This corresponds to the normal application operation. All functions are available in this mode (watchdog, wake-up input reading through SPI, HS activation, and CAN communication). Watchdog software is running and must be periodically cleared through SPI. Standby Mode In Standby mode, only the VDDregulator is ON. The V2 regulator is turned OFF by disabling the V2CTRL terminal. The CAN interface is not able to send messages. If a CAN message is received, the CANWU bit is set. Other functions available are L0:L3 input reading through SPI and HS activation. Watchdog is running. Sleep Mode In Sleep mode, the VDD and V2 regulators are OFF. Current from the VSUP terminal is reduced. In Sleep mode, the 33742 can be awakened by L0:L3 inputs, by cyclic sense of the L0:L3 inputs, by the automatic forced wake-up timer, and from the CAN physical interface receiving an incoming CAN message. When a wake-up occurs, the 33742 goes first into the Reset mode before entering Normal Request mode. Stop Mode The V2 regulator is turned OFF by disabling the V2CTRL terminal. The VDD regulator is activated in a special low power mode, allowing the delivery of a few mA. The objective is to maintain power on the MCU of the application while the MCU is turned into power-saving condition (i.e, Stop or Wait modes). In Stop mode, the device supply current from VPWR is very low. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA When the application is in Stop mode (both MCU and 33742), the application can wake up from either the 33742 side (for example, cyclic sense, forced wake-up, CAN message, wake-up inputs, and overcurrent on VDD) or the MCU side (key wake-up, etc.). Stop mode is always selected by SPI. In Stop mode, the watchdog software may be either running or not running depending upon selection by SPI (Reset Control Register [RCR], bit WDSTOP). To clear the watchdog if it is running, the 33742 must be awakened by the CS terminal (SPI wake-up). In Stop mode, the 33742 wake-up capability is identical to that in Sleep mode, with the addition of CS and VDD overcurrent wakeup. Refer to Table 2, page 20. Application Wake-Up from 33742 Side When the application is in Stop mode, it can wake up from the 33742 side. When a wake-up is detected by the 33742 (for example, CAN, wake-up input), the 33742 turns itself into Normal Request mode and generates an interrupt pulse at the INT terminal. Application Wake-Up from MCU Side When the application is in Stop mode, the wake-up event may come from the MCU side. In this case the MCU signals to the 33742 by a LOW-to-HIGH transition on the CS terminal. Then the 33742 goes into Normal Request mode and generates an interrupt pulse at the INT terminal. Stop Mode Current Monitor If the VDD output current exceeds an internal threshold (IDDS-WU), the 33742 goes automatically into Normal Request mode and generates an interrupt at the INT terminal. The interrupt is not maskable and the INTR register will have no flag set. Interrupt Generation When Wake-Up from Stop Mode When the 33742 wakes up from Stop mode, it first enters the Normal Request mode before generating a pulse (10 s typical) on the INT terminal. These interrupts are not maskable, and the wake-up event can be read through the SPI registers, CANWU bit in the CAN Register (CANR), and LCTRx bit in the Wake-Up Register (WUR). In case of wake-up from Stop mode overcurrent or from forced wake-up, no bit is set. After the INT pulse, the 33742 accepts SPI command after a time delay (t S-1STSPI). Watchdog Software in Stop Mode If watchdog is enabled, the MCU has to wake up independently of the 33742 before the end of the 33742 watchdog time. In order to do this, the MCU must signal the wake-up to the 33742 through the SPI wake-up (CS activation). The 33742 then wakes up and jumps into the Normal Request mode. The MCU has to configure the 33742 to go to either Normal or Standby mode. The MCU can then decide to go back to the Stop mode. Freescale Semiconductor, Inc... For More Information On This Product, Go to: www.freescale.com 33742 21 Freescale Semiconductor, Inc. If no MCU wake-up occurs within the watchdog timing the 33742 activates the RST terminal and jumps into the Normal Request mode. The MCU can then be initialized. Stop Mode Enter Command Stop mode is entered at the end of the SPI message at the rising edge of the CS. (Refer to the t CS-STOP data in the Dynamic Electrical Characteristics table on page 13.) Once Stop mode is entered, the 33742 can wake up from the VDD regulator overcurrent detection. In order to allow time for the MCU to complete the last CPU instruction, allowing the MCU to enter its low power mode, a deglitcher time of 40 s typical is implemented. Figure 8, page 22, depicts the operation of entering the Stop mode. SPI Stop/Sleep Command Freescale Semiconductor, Inc... SPI CS t CS-STOP t IDD-DGLT 33742 in Normal or Standby mode 33742 in Stop mode. No IDD over IDD-DGLT 33742 in Stop mode. IDD over IDD-DGLT Figure 8. Entering Stop Mode RST and WDOG Terminals, Software Watchdog Operations Watchdog Software (Selectable Watchdog Window or Watchdog Timeout) Watchdog software is used in the 33742 Normal and Standby modes for monitoring the MCU. Watchdog may be either watchdog window or watchdog timeout, selectable by SPI (TIM1 subregister, bit WDW). Default is watchdog window. The watchdog period may be set from 10 ms to 350 ms (TIM1 subregister, bits WDT0 and WDT1). When watchdog window is selected, the closed window is the first part of the selected period, and the open window is the second part of the period. (Refer to Timing Register (TIM1/2) beginning on page 43.) Watchdog can only be cleared within the open window time. Any attempt to clear watchdog in the closed window will generate a reset. Watchdog is cleared through SPI by addressing the TIM1 subregister. RST Terminal Description A reset output is available to reset the MCU. Causes of reset are the following: * VDD Falling Out of Range--If VDD falls below the reset threshold (V RSTTH), the RST terminal is pulled LOW until VDD returns to the normal voltage. * Power-ON Reset--At 33742 power-on or wake-up from Sleep mode, the RST terminal is maintained LOW until VDD is within its operation range. * Watchdog Timeout--If watchdog is not cleared, the 33742 will pull the RST terminal LOW for the duration of the reset time (t RSTDUR). 33742 22 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. Reset and Watchdog Operation Table 3 describes watchdog and reset output modes of operation. RST is activated in the event VDD fall or watchdog is not triggered. WDOG output is active LOW as soon as RST goes LOW and stays LOW as long as the watchdog is not properly reactivated by SPI. The WDOG output terminal is a push-pull structure that can drive external components of the application; for instance, to signal MCU wrong operation. Figure 9 illustrates the device behavior in the event the TIM1 register in not properly accessed. In this case a software reset occurs, and the WDOG terminal is set LOW until the TIM1 register is properly accessed. Table 3. Watchdog and Reset Output Operation Events Device Power-Up VDD Normal, Watchdog Properly Triggered VDD < RSTTH Watchdog Timeout Reached WDOG Output LOW to HIGH HIGH HIGH LOW (Note 41) RST Output LOW to HIGH HIGH LOW LOW Notes 41. WDOG stays LOW until the TIM1 register is properly addressed through SPI. Freescale Semiconductor, Inc... VDD RST WDOG Watchdog Timeout Watchdog Period SPI Watchdog Clear SPI CS TIM1 register addressed. Figure 9. RST and WDOG Output Operation Wake-Up Capabilities Several wake-up capabilities are available to the 33742 when it is in Sleep or Stop mode. When a wake-up has occurred, the wake-up event is stored in the Wake-Up Register (WUR) or the CAN register. The MCU can then access the wake-up source. The wake-up options are selectable through SPI while the 33742 is in Normal or Standby mode and prior to entering low power mode (Sleep or Stop mode). When a wakeup occurs from Sleep mode, the 33742 activates VDD. It generates an interrupt if wake-up occurs from Stop mode. Wake-Up from Wake-Up Inputs (L0:L3) Without Cyclic Sense The wake-up lines are dedicated to sense the state of external switches and if changes occur to wake up the MCU (in Sleep or Stop modes). Wake-up terminals L0:L3 are able to handle 40 VDC. The internal threshold is 3.0 V typical and these inputs can be used as an input port expander. The wakeup input states are read through SPI (WUR register). In order to select and activate direct wake-up from the L0:L3 inputs, the WUR register must be configured with the appropriate level sensitivity. Additionally, the Low Power Control (LPC) Register must be configured with 0xx0 data (bits LX2HS and HSAUTO are set to 0). Level sensitivity is selected by the WUR register. Level sensitivity is configured by L0:L3 input pairs: L0 and L1 level sensitivity are configured together, while L2 and L3 are configured together. Cyclic Sense Wake-Up (Cyclic Sense Timer and Wake-Up Inputs L0:L3) The 33742 can wake up upon state change of one of the four wake-up input lines (L0:L3) while the external pullup or pulldown resistor of the switches associated with the wake-up input lines are biased with HS VSUP switch. The HS switch is activated in Sleep or Stop modes from an internal timer. Cyclic Sense and Forced Wake-Up are exclusive. If Cyclic Sense is enabled, Forced Wake-Up cannot be enabled. In order to select and activate the cyclic sense wake-up from the L0:L3 inputs, the WUR register must be configured with the appropriate level sensitivity, and the LPC register must be configured with 1xx1 data (bit LX2HS set at 1 and bit HSAUTO set at 1). The wake-up mode selection (direct or cyclic sense) is valid for all four wake-up inputs. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33742 23 Freescale Semiconductor, Inc. Forced Wake-Up The 33742 can wake up automatically after a predetermined time spent in Sleep or Stop mode. Cyclic Sense and Forced Wake-up are exclusive. If Forced Wake-Up is enabled (FWU bit set to 1 in the LPC register), Cyclic Sense cannot be enabled. CAN Interface Wake-Up The 33742 incorporates a high-speed 1.0 Mbps CAN physical interface. It is compatible with ISO 11898-2. The control of the CAN physical interface operation is accomplished through the SPI. CAN modes are independent of the 33742 operation modes. The 33742 can wake up from a CAN message if the CAN wake-up is enabled. Refer to the section titled CAN BUS MODULE DESCRIPTION beginning on page 29 for details of the wake-up detection. SPI Wake-Up The 33742 can be awakened by the CS terminal in Sleep or Stop modes. Wake-up is detected by the CS terminal transition from LOW to HIGH level. In Stop mode, this corresponds with the condition where the MCU and the 33742 are in Stop mode and when the application wake-up event comes through the MCU. 33742 Power-Up and 33742 Wake-Up from Sleep Mode After device or system power-up, or after the 33742 wakes up from Sleep mode, the 33742 enters into the Reset mode prior to moving into Normal Request mode. Figure 10 shows the device state diagram and Figure 11, page 25, shows device behavior after power-up sequence. Freescale Semiconductor, Inc... Watchdog: Timeout OR VDD Low Watchdog: Timeout & Nostop & !BATFAIL Reset Counter (3.4 ms) Expired 2 Reset 1 Normal Request 4 SPI: Standby and Watchdog Trigger (Note 42) 3 1 Standby Nostop and SPI: Sleep & CS LOW to HIGH Transition Nostop and SPI: Sleep & CS LOW to HIGH 33742 Power-Up Wake-Up Ti m eo ut O R Power Down V DD Lo w 2 (N o te 1 43 ) Stop Watchdog: Timeout OR VDD Low SPI: Stop & CS LOW to HIGH Transition Normal 1 Wake-Up (VDD High Temperature OR [VDD Low > 100 ms & VSUP > BFew]) & Nostop & !BATFAIL 1 2 3 4 Denotes priority Watchdog: Timeout = TIM1 register not written before watchdog timeout period expired, or watchdog written in incorrect time window if watchdog window selected (except Stop mode). In Normal Request mode, timeout is 355 ms p2.2 (350 ms p3) ms. SPI: Sleep = SPI write command to MCR register, data sleep SPI: Stop = SPI write command to MCR register, data stop SPI: Normal = SPI write command to MCR register, data normal SPI: Standby = SPI write command to MCR register, data standby SPI: Normal g: SPI: Standby ch do SP I: H Sto ig p h& Tr C an S si Lo ti o w n to W at VDD Low OR Watchdog: Timeout 350 ms & Nostop g: do ch r at e W rigg T Sleep State Machine Description Nostop = Nostop bit = 1 !Nostop = Nostop bit = 0 BATFAIL = Batfail bit = 1 !BATFAIL = Batfail bit = 0 VDD Overtemperature = VDD thermal shutdown occurs VDD LOW = VDD below reset threshold VDD LOW > 100 ms = VDD below reset threshold for more than 100 ms Watchdog: Trigger = TIM1 subregister write operation VSUP > BFew = VSUP > Battery Fail Early Warning (6.1 V typical) Notes 42. These two SPI commands must be sent consecutively in this sequence. 43. If watchdog activated. Figure 10. 33742 State Diagram (Not Valid in Debug Modes) 33742 24 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. Power-Up Behavior after power-up if no trigger appears Behavior after reset of BATFAIL if no trigger appears Reset Normal Request No Trigger Yes Batfail Yes No No No Stop Yes Sleep Freescale Semiconductor, Inc... Normal Figure 11. Behavior at 33742 Power-Up Debug Mode: Hardware and Software Debug with the 33742 When the 33742 is mounted on the same printed circuit board as the MCU it supplies, both application software and 33742 dedicated routines must be debugged. The following features permit software debugging by allowing the possibility of disabling the 33742 internal software watchdog timer. Device Power-Up, Reset Terminal Connected to VDD At 33742 power-up, VDD voltage is provided; however, if no SPI communication occurs to configure the device, a reset occurs every 350 ms. In order to allow software debug and avoid MCU reset, the RST terminal can be connected directly to VDD by a jumper. Debug Modes with Software Watchdog Disabled Though SPI (Normal Debug, Standby Debug, and Stop Debug) The watchdog software can be disabled through SPI. To avoid unwanted watchdog disable while limiting the risk of disabling the watchdog during 33742 normal operation, watchdog disable must be done using the following sequence: * Step 1-Power down the 33742. * Step 2-Power up the 33742. This sets the BATFAIL bit, allowing the 33742 to enter Normal Request mode. * Step 3-Write to the TIM1 subregister to allow the 33742 to enter Normal mode. * Step 4-Write to the MCR register with data 0000. This enables the debug mode. Complete SPI byte is 0001 0000. * Step 5-Write to the MCR register normal debug. SPI byte is 0001 x101. Important While in debug mode, the 33742 can be used without having to clear the watchdog on a regular basis to facilitate software and hardware debug. * Step 6-To leave the debug mode, write 0000 to the MCR register. At Step 2, the 33742 is in Normal Request. Steps 3, 4, and 5 should be completed consecutively and within the 350 ms time period of the Normal Request mode. If not, the 33742 will go into Reset mode and enter Normal Request again. Figure 12, page 26, illustrates debug mode selection. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33742 25 Freescale Semiconductor, Inc. VSUP VDD BATFAIL TIM1(Step 3) SPI MCR (Step 4) Debug Mode SPI: Read BATFAIL 33742/33742S in Debug mode. No Watchdog Figure 12. Entering Debug Mode 33742/33742S not in Debug mode. Watchdog ON MCR (Step 5) MCR (Step 6) Freescale Semiconductor, Inc... When the 33742 is in debug mode and has been set into Stop Debug or Sleep, a wake-up causes the 33742 to enter the Normal Request mode for 350 ms. To avoid having the 33742 generate a reset (enter Reset mode), the desired next debug mode (Normal Debug or Standby Debug) should be configured within the 350 ms time period of the Normal Request mode. To avoid entering debug mode after a power-up, first read the BATFAIL bit (MCR read) and write 0000 into the MCR register. Figure 13 below and Figure 14, page 27, show the detailed operation of the 33742 once the debug mode has been selected. Watchdog: Timeout 350 ms Normal Request Watchdog: Trigger Reset Counter (3.4 ms) Expired Reset Power Down Normal SPI: MCR (0000) and Normal Debug Normal Debug SPI: MCR (0000) and Standby Debug Standby Debug Figure 13. Transitions to Enter Debug Modes 33742 26 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. Watchdog: Timeout 350 ms Stop (1) R Wake-Up Normal Request SPI: Standby & Watchdog: Trigger Reset Counter (3.4 ms) Expired Reset R Wake-Up Sleep & !BATFAIL & NOSTOP & SPI: Sleep R Wa tc W ak eU p hd o g: T rig g R R er R SPI: Stop SPI: Standby Debug Freescale Semiconductor, Inc... SPI: Stop Debug & CS Low to High Transition E g SP ma l De bu E Standby Debug SPI: Standby Debug SPI: Normal Debug Normal Debug R R (1) If Stop mode is entered, it is entered without watchdog, no matter the WDSTOP bit. (E) Debug mode entry point (Step 5 of the Debug mode entering sequence). (R) Represents transitions to Reset mode due to VDD low. Figure 14. Simplified 33742 State Diagram in Debug Modes MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA SPI: Normal Debug I: St an :N or db y SP I D eb ug Stop Debug Standby Normal For More Information On This Product, Go to: www.freescale.com 33742 27 Freescale Semiconductor, Inc. MCU Flash Programming Configuration To allow for the possibility of downloading software into the application memory (MCU EEPROM or Flash), the 33742 is capable of allowing (1) VDD to be forced by an external power supply to 5.0 V and (2) the RST and the WDOG outputs to be forced by external signal sources to 0 V or 5.0 V, both without damaging the device. This allows, for example, the complete application board to be supplied by external power supply and external signal to be applied to the reset terminals. No functions of the 33742 are operating. Figure 15 illustrates a typical configuration for the connection of programming and debugging tools. VDD VSUP (Open or > 5.0 V The VDD regulator has an internal pass transistor between VSUP and the VDD output terminal. Biasing the VDD output terminal with a voltage greater than VSUP potential will force current through the body diode of the internal pass transistor to the VSUP terminal. Therefore, VSUP should be left open or forced to a value equal to or above VDD. The RST terminal is periodically pulled LOW for t RSTDUR time (device in reset mode), before being pulled to VDD for 350 ms typical (device in Normal Request mode). During the time reset is LOW, the RST terminal sinks 5.0 mA maximum (IPDW). Freescale Semiconductor, Inc... RST 33742 WDOG MCU with Flash Memory 5.0 V Programming Bus Programming Tool Note External supply and sources applied to VDD, RST, and WDOG test points on application circuit board. Figure 15. Simplified Schematic for Microcontroller Flash Programming 33742 28 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. CAN BUS MODULE DESCRIPTION Introduction The 33742 features a high-speed CAN physical interface for bus communication between 60 kbps up to 1.0 Mbps. Figure 16 V2 V2 SPI control TXD V2 V2 Driver QH CANH CANH Line RXD Differential Receiver 2.5 V Bus Termination (60 ) CANL Line V2 Driver SPI Control VSUP Internal Wake-Up Signal Wake-Up Pattern Recognition SPI Control Wake-Up Receiver QL CANL below is a simplified block diagram of the CAN interface of the 33742. Freescale Semiconductor, Inc... Figure 16. Simplified Block Diagram of CAN Interface CAN Interface Supply The supply voltage for the CAN driver is the V2 terminal. The CAN interface has also a supply path from the battery line, through the VSUP terminal. This path is used in CAN Sleep mode to allow wake-up detection. During CAN communication (transmission and reception), the CAN interface current is sourced from the V2 terminal. During CAN low power mode, the current is sourced from the VSUP terminal. CAN Driver Operation in TXRX Mode When the CAN interface of the 33742 is in TXRX mode, the driver has two states: recessive or dominant. The driver state is controlled by the TXD terminal. The bus state is reported through the RXD terminal. When TXD is HIGH, the driver is set in recessive state, and CANH and CANL lines are biased to the voltage set at V2 divided by 2, or approximately. 2.5 V. When TXD is LOW, the bus is set into dominant state: CAN L and CANH drivers are active. CANL is pulled to ground, and CANH is pulled HIGH toward 5.0 V (voltage at V2). The RXD terminal reports the bus state: CANH minus CANL voltage is compared versus an internal threshold (a few hundred millivolts). If CANH minus CANL is below the threshold, the bus is recessive and RXD is set HIGH. If CANH minus CANL is above the threshold, the bus is dominant and RXD is set LOW. This is illustrated in Figure 16, page 29. Main Operation Modes Description The CAN interface of the 33742 has two main operation modes: TXRX and Sleep mode. The modes are controlled by the CAN SPI Register. In the TXRX mode, which is used for communication, four different slew rates are available for the user. In the Sleep mode, the user has the option of enabling or disabling the remote CAN wake-up capability. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33742 29 Freescale Semiconductor, Inc. TXD CANH Typ 2.5 V VCANH -VCANL > 900 mV VCANH -VCANL < 500 mV CANL Typ 2.5 V Freescale Semiconductor, Inc... RXD CAN Recessive State CAN Dominant State CAN Recessive State Figure 17. CAN Interface Levels TXD and RXD Terminals The TXD terminal has an internal pullup to V2. The state of TXD depends on the V2 status. RXD is a push-pull structure, supplied by V2. When V2 is set at 5.0 V and CAN is TXRX mode, RXD reports bus status. For details, refer to Table 2, page 20, Table 4, below, and Table 5, page 31. CAN TXRX Mode and Slew Rate Selection The slew rate selection is done via CAN register (refer to Tables 16 through 18 on page 40). Four slew rates are available, and controls the recessive to dominant and dominant to recessive transitions. The delay time from TXD terminal to CAN bus, from CAN bus to RXD and the TXD to RXD loop time is affected by the slew rate selection. Table 4. CAN Interface/33742 Modes and Terminal Status--Operation with Ballast on V2 (Note 44) Mode Unpowered Reset (with Ballast) Normal Request (with Ballast) Normal Normal CAN Mode (Controlled by SPI) - - - Sleep Normal Slew Rate 0, 1, 2, 3 V2 Voltage 0V 0V 0V 5.0 V 5.0 V TXD Terminal LOW LOW LOW 0V Internal Pullup to V2 RXD Terminal LOW LOW LOW 5.0 V Report Bus State HIGH if Bus Recessive, LOW if dominant LOW LOW LOW CANH/CANL (Disconnected from Other Node) Floating to GND Floating to GND Floating to GND Floating to GND Bus Recessive CANH = CANL = 2.5 V Floating to GND Floating to GND Floating to GND CAN Communication NO NO NO NO YES Standby with External Ballast Sleep Stop Normal or Sleep Sleep Sleep 0V 0V 0V LOW LOW LOW NO NO. Wake-up if enabled NO. Wake-up if enabled Notes 44. See also Figure 28, page 46. 33742 30 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. Table 5. CAN Interface/33742 Modes and Terminal Status--Operation without Ballast on V2 (Note 45) Mode Unpowered Reset (with Ballast) Normal Request without Ballast. V2 Connected to VDD Standby without External Ballast, V2 connected to VDD Normal without External Ballast. V2 Connected to VDD Normal without External Ballast, V2 Connected to VDD Sleep Stop CAN Mode (Controlled by SPI) - - - V2 Voltage 0V 0V 5.0 V TXD Terminal LOW LOW LOW RXD Terminal LOW LOW 5.0 V CANH/CANL (Disconnected from Other Node) Floating to GND Floating to GND Floating to GND CAN Communication NO NO NO Normal or Sleep 5.0 V 0V 5.0 V Floating to GND NO Normal Slew Rate 0, 1, 2,3 Sleep 5.0 V 5.0 V 5.0 V Freescale Semiconductor, Inc... Bus Recessive CANH = CANL = 2.5 V Floating to GND YES 5.0 V 0V 5.0 V NO Sleep Sleep 0V 0V LOW LOW LOW LOW Floating to GND Floating to GND NO. Wake-up if enabled NO. Wake-up if enabled Notes 45. See also Figure 29, page 47. the CAN is in Sleep mode, the current sourced from V2 is extremely low. In most cases the V2 voltage is off; however, the CAN can be placed into Sleep mode even with 5.0 V applied on V2. In CAN Sleep mode, the CANH and CANL drivers are disabled, and the receiver is also disabled. CANH and CANL are high ohmic termination to ground. CAN Signals in TXRX and Sleep Modes When the CAN interface is set back into TXRX mode by an SPI command, CAN H and CANL are set in recessive level. This is illustrated in Figure 18. CAN Sleep Mode The 33742 offers two CAN Sleep modes: * Sleep mode with CAN wake-up enable: detection of incoming CAN message and SBC wake-up. * Sleep mode with CAN wake-up disable: no detection of incoming CAN message. The CAN Sleep mode is done via the CAN SPI register. In CAN Sleep mode (with wake-up enable or disable), the CAN interface is internally supplied from the VSUP terminal. The voltage at V2 terminal can be either 5.0 V or turned off. When TXD CANH Dominant CANH 2.5 V CANL CANL Dominant Ground CANL/CANH Recessive RXD CAN in Sleep Mode (Wake-Up Enable or Disable) CAN in TXRX Mode (Controlled by SPI Command) CAN in TXRX Mode Figure 18. CAN Signals in TXRX and Sleep Modes MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33742 31 Freescale Semiconductor, Inc. CAN in Sleep Mode with Wake-Up Enable When the CAN interface is in Sleep mode with wake up enable, the CAN bus traffic is detected. The CAN bus wake up is a pattern wake up. Pattern Wake-Up In order to wake up the CAN interface, the following criteria must be fulfilled: * The CAN interface wake-up receiver must receive a series of three consecutive valid dominant pulses, each of them has to be longer than 500 ns and shorter than 500 s. * The distance between 2 pulses must be lower than 500 s. * The three pulses must occur within a time frame of 1.0 ms. The pattern wake-up of the 33742 CAN interface allow wake-up by any CAN message content. Figure 19 below illustrates the CAN signals during a CAN bus Sleep state and wake-up sequence. Freescale Semiconductor, Inc... TXD CANH Dominant CANH 2.5 V CANL CANL Dominant RXD CAN in TXRX Mode Ground CAN Bus Sleep State CANL Dominant CANL Dominant CANL Dominant CANL/CANH Recessive CANH Dominant Pulse # 1 CANH Dominant Pulse # 2 CANH Dominant Pulse # 3 Incoming CAN Message CAN in Sleep Mode (Wake-Up Enable) WU Receiver Min 500 ns Max 500 s Internal Wake-Up Signal Figure 19. CAN Bus Signal During Can Sleep State and Wake-Up Sequence 33742 32 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. Figure 20 illustrates how the wake-up signal is generated. First the CAN signal is detected by a low consumption receiver (WU receiver). Then the signal passes through a pulse width filter, which discards the undesired pulses. The pulse must have a width bigger than 0.5 s and smaller than 500 s to be accepted. When a pulse is discarded, the pulse counter is reset and no wake-up signal is generated. When a pulse is accepted, the pulse counter is incremented and, after three pulses, the internal wake-up signal is asserted. Each one of the pulses must be spaced by no more than 500 s. If not, the counter will be reset and no wake-up signal will be generated. This is accomplished by the wake-up timeout generator. The wake-up cycle is completed (and the wake-up flag reset) when the CAN interface is brought to CAN Normal mode. CANH CANL WU Receiver Pulse Width Filter Pulse OK Counter RST Timeout Latch RST Internal Wake-Up Signal Freescale Semiconductor, Inc... Narrow Pulse + Timeout Generator Figure 20. Wake-Up Functional Block Diagram CAN Wake-Up Report The CAN wake-up reports depend upon the 33742 low power mode. If the 33742 is placed into Sleep mode (VDD and V2 off), the CAN wake-up or any wake-up results in VDD regulator turn on, leading to MCU supply turn on and reset release. If the 33742 is in Stop mode (V2 off and VDD active), the CAN wake-up or any wake-up is signalled by a pulse on the INT output. In addition the CAN-WU bit is set in the CAN register. Standby If the 33742 is in Normal or Standby mode and the CAN interface is in Sleep mode with wake-up enable, the CAN wakeup is reported by the bit CANWU in the CAN register. In the event the 33742 is in Normal mode and CAN Sleep mode with wake-up enable, it is recommended that the user check for the CAN WU bit prior to setting the 33742 in Sleep or Stop mode in case bus traffic has occurred while the CAN interface was in Sleep mode. After CAN wake-up, a flag is set in the CAN register. Bit CAN-WU reports the CAN wake-up event while the 33742 was in Sleep or Stop mode. This bit is set until the CAN is in placed by SPI command into TXRX mode and the CAN register read. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33742 33 Freescale Semiconductor, Inc. CAN Bus Diagnostic The 33742 can diagnose CANH or CANL lines short to GND, short to VSUP , and short to VDD. As illustrated in Figure 21, several single-ended comparators are implemented on the CANH and CANL bus lines. These comparators monitor the bus level in recessive and dominant states. The information is then managed by a logic circuit to properly determine the failure and report it. Table 6 indicates the state of the comparators in the event of bus failure and the state of the drivers; that is, whether they are recessive or dominant. H5 Hb TXD Hg Logic Lg Vr5 VSUP (12 V-14 V) Vrvb VDD Vrvb (VSUP - 2.0 V) CANH VDD (5.0 V) Vr5 (VDD - 0.43 V) CANH Dominant Level (3.6 V) Recessive Level (2.5 V) Vrg (1.75 V) CANL Dominant Level (1.4 V) GND (0 V) Figure 21. CAN Bus Simplified Structure Vrg Freescale Semiconductor, Inc... Diagnostic Vrg Lb L5 Vrvb Vr5 CANL Table 6. Short to GND, Short to VSUP , and Short to 5.0 V Detection Truth Table Failure Description No failure CANL to GND CANH to GND Driver Recessive State Lg (Threshold 1.75 V) 1 0 0 Hg (Threshold 1.75 V) 1 0 0 Driver Dominant State Lg (Threshold 1.75 V) 0 0 0 Hg (Threshold 1.75 V) 1 1 0 Hb (Threshold VSUP -2.0 V) 0 1 1 H5 (Threshold VDD -0.43 V) 0 1 1 Lb (Threshold VSUP -2.0 V) Hb (Threshold VSUP -2.0 V) Lb (Threshold VSUP -2.0 V) No failure CANL to VSUP CANH to VSUP 0 1 1 L5 (Threshold VDD -0.43 V) No failure CANL to VDD CANH to VDD 0 1 1 0 1 1 0 1 0 H5 (Threshold VDD -0.43 V) L5 (Threshold VDD -0.43 V) 0 1 1 0 1 0 33742 34 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. Detection Principle In the recessive state, if one of the two bus lines is shorted to GND, VDD, or VSUP, then voltage at the other line follows the shorted line due to bus termination resistance and the high impedance of the driver. For example, if CANL is shorted to GND, CANL voltage is zero, and CANH voltage, as measured by the Hg comparator, is also close to zero. In the recessive state the failure detection to GND or VSUP is possible. However, it is impossible to distinguish which bus line, CANL or CANH, is shorted to GND or VSUP. In the dominant state, the complete diagnostic is possible once the driver is turned on. CAN Bus Failure Reporting In the CAN register, bits D2 and D1 (CAN-F and CAN-UF, respectively) are used to signal bus failure. Bit D2 reports a bus failure and bit D1 indicates if the failure is identified or not (bit D1 is set to 1 if the error is not identified). When the detection mechanism is complete, the error will be fully detected and reported in the TIM1/2 and LPC registers and bit D1 will be reset to 0. Number of Samples for Proper Failure Detection The failure detector requires at least one cycle of recessive and dominant state to properly recognize the bus failure. The error will be fully detected after five cycles of recessivedominant states. As long as the failure detection circuitry has not detected the same error for five recessive-dominant cycles, the bit "non-identified failure" (CAN-UF) will be set. Freescale Semiconductor, Inc... CANL bus line failures (for example, CANL short to GND) is reported in the SPI register TIM1/2. CANH bus line (for example, CANH short to VSUP) is reported in the LPC register. In addition CANF and CAN-UF bits in the CAN register indicate that a CAN bus failure has been detected. Non-Identified and Fully Identified Bus Failures As indicated in Table 6, page 34, when the bus is in a recessive state it is possible to detect an error condition; however, is it not possible to fully identify which error. This is called "non-identified" or "under-acquisition" bus failure. If there is no communication (i.e., bus idle), it is still possible to warn the MCU that the device has started to detect a bus failure. TXD Diag Logic TXD Driver CANL CANH Diff Output VDD RXD Sense RXD Driver Diff RXD Permanent Recessive Failure The purpose of this detection mechanism is to diagnose an external hardware failure at the RXD output terminal and to ensure that a permanent failure at the RXD terminal does not disturb network communication. In the event RXD is shorted to a permanent high level signal (i.e., 5.0 V), the CAN protocol module within the MCU cannot receive any incoming message. Additionally, the CAN protocol module cannot distinguish the bus idle state and could start communication at any time. To prevent this, an RXD failure detection, as illustrated in Figure 22 and explained below, is necessary. Sampling Sampling Sampling Sampling RXD Short to VDD 2.0 V VDD RXD CANH 60 CANL RXD Output RXD Flag Prop Delay RXD Flag Latched Note RXD Flag is neither the RXPR bit in the LPC register nor the CAN-F bit in the INTR register. Figure 22. RXD Path and RXD Permanent Recessive Detection Principle RXD Failure Detection The 33742 senses the RXD output voltage at each LOW-toHIGH transition of the differential receiver. Excluding internal propagation delay, RXD output should be LOW when the differential receiver is LOW. In the event RXD is shorted to 5.0 V (e.g., to VDD), RXD will be tied to a high level and the RXD short to 5.0 V can be detected at the next LOW-to-HIGH transition of the differential receiver. Compete detection requires three samples. When the error is detected, the flag is latched and the CAN driver is disabled. The error is reported through the SPI register LPC, bit RXPR. Recovery Condition The internal recovery is completed by the sampling of a correct low level at TXD, as illustrated in Figure 23, page 36. As soon as the RXD permanent recessive is detected, the RXD driver is deactivated and a weak pulldown current source 33742 35 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. is activated in order to allow recovery conditions. The driver stays disabled until the failure is cleared (RXD no longer permanent recessive) and the bus driver is activated by an SPI register command (write 1 to the CANCLR bit in the CAN register). CANL CANH Diff Output Sampling RXD Output RXD Short to VDD RXD no longer shorted to VDD Sampling Recovery The TXD permanent dominant is used and activated also in case of TXD short to RXD. The recovery condition for TXD permanent dominant (recovery means the reactivation of the CAN drivers) is done by an SPI command and is controlled by the MCU. The driver stays disabled until the failure is cleared (TXD no longer permanent dominant) and the bus driver is activated by an SPI register command (write 1 to bit CANCLR in the CAN register). TXD to RXD Short Circuit Failure Principle In the event TXD is shorted to RXD when an incoming CAN message is received, RXD is set LOW. Consequently, the TXD terminal is LOW and drives CANH and CANL into the dominant state. The bus is stuck in dominant and no further communication is possible. Detection and Recovery RXD Flag Latched Freescale Semiconductor, Inc... RXD Flag Note RXD Flag is neither the RXPR bit in the LPC register nor the CAN-F bit in INTR register. Figure 23. RXD Recovery Conditions TXD Permanent Dominant Failure Principle In the event TXD is set to a permanent low level, the CAN bus is set into dominant level, and no communication is possible. The 33742 has a TXD permanent timeout detector. After timeout, the bus driver is disabled and the bus is released in a recessive state. The TXD permanent dominant failure is reported in the TIM1 register. The TXD permanent dominant timeout will be activated and release the CANL and CANH drivers. However, at the next incoming dominant bit, the bus will then be stuck again in dominant. In order to avoid this situation, the recovery of the failure (recovery means the reactivation of the CAN drivers) is done by an SPI command and controlled by the MCU. Internal Error Output Flags There are internal error flags to signal whenever thermal protection is activated or overcurrent detection occurs on the CANL or CANH terminals (bit THERM-CUR). The errors are reported in the CAN register. 33742 36 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. DEVICE FAULT OPERATION Table 7 describes the relationship between device fault or warning and the operation of the VDD, V2, CAN, and HS interface. Table 7. Fault/Warning Fault/Warning Battery Fail VDD Temperature Prewarning VDD Overtemperature VDD Turn OFF Warning flag only. Leave as is Turn OFF VDD regulator enters linear mode. VDD undervoltage reset may occurs. VDD overtemperature prewarning or shutdown may occur VDD undervoltage reset occurs. VDD overtemperature prewarning or shutdown may occur ON No change No change No change No change No change V2 Turn OFF No change Turn OFF Turn OFF if VDD undervoltage reset occurs CAN Turn OFF due to V2. No communication No change Turn OFF due to V2. No communication If V2 is OFF, turn OFF and no communication HS OFF No change OFF Turn OFF if VDD undervoltage reset occurs Freescale Semiconductor, Inc... VDD Overcurrent VDD Short Circuit Turn OFF Turn OFF due to V2. No communication OFF Watchdog Reset V2LOW (e.g., V2 < 4.0 V) HS Overtemperature HS Overcurrent VSUP LOW CAN Overtemperature Turn OFF V2 out of range No change No change No change No change Turn OFF due to V2. No communication Turn OFF due to V2 low No change No change No change Disable. As soon as temperature falls, CAN is re-enabled automatically (Note 46) No communication (Note 48) Communication OK Communication OK Communication OK No communication (Note 48) No communication (Note 48) OFF No change OFF HS overtemperature may occur No change No change CAN Overcurrent CANH Short to GND CANH Short to VDD CANH Short to VSUP CANL Short to GND CANL Short to VDD CANL Short to VSUP No change No change No change No change No change No change No change No change No change (Note 47) No change No change No change No change No change No change No change No change No change No change No change No change Notes 46. Refer to descriptions of CANH and CANL short to GND, VDD, and VSUP elsewhere in table. 47. 48. Peak current 150 mA during TXD dominant only. Due to loss of communication, CAN controller reaches bus OFF state. Average current out of V2 is below 10 mA. Overcurrent might be detected. Bit THERM-CUR set in CAN register. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33742 37 Freescale Semiconductor, Inc. SPI INTERFACE AND REGISTER DESCRIPTION Data Format Description Figure 24 illustrates a register, an 8-bit SPI. The first three bits are used to identify the internal 33742 register address. Bit 4 is a read/write bit. The last four bits are data sent from the MCU to the 33742 or read back from the 33742 to the MCU. The state of the MISO has no significance during the write operation. However, during the read operation the final four bits of MISO have meaning; namely, they contain the content of the accessed register. Table 8 lists the possible reset conditions. Table 8. Possible Reset Conditions Condition 33742 Reset 33742 Mode Transition Name POR NR2R NR2N NR2STB N2R Definition Power-ON Reset Normal Request to Reset Mode Normal Request to Normal Mode Normal Request to Standby Mode Normal to Reset Mode Standby to Reset Mode Stop to Reset Mode Stop to Normal Request 33742 in Reset Mode Freescale Semiconductor, Inc... MISO Bit 7 Bit 6 A2 A1 Bit 5 A0 Bit 4 Bit 3 R/W D3 Bit 2 D2 Bit 1 D1 Bit 0 D0 MOSI STB2R STO2R STO2NR Address Data 33742 Mode RESET Note Read operation: R/W bit = 0; Write operation: R/W = 1. Register Descriptions The following tables in this section describe the SPI register list and register bit meaning. Register reset value is also described, along with the reset condition. Reset condition is the condition causing the bit to be set at the reset value. Figure 24. Data Format Description Table 9. List of Registers Register MCR RCR CAN Address $000 $001 $010 Formal Name and Link Mode Control Register (MCR) on page 39 Reset Control Register (RCR) on page 40 CAN Register (CAN) on page 40 Input/Output Register (IOR) on page 41 Wake-Up Register (WUR) on page 42 Timing Register (TIM1/2) on page 43 Comment and Use Write Selection for Normal, Standby, Sleep, Stop, and Debug modes Read BATFAIL, general failure, VDD prewarning, and Watchdog flag Configuration for reset voltage level, CAN Sleep and Stop modes CAN slew rate, Sleep and Wake-Up enable/disable modes, drive enable after failure HS (High Side switch) control in Normal and Standby mode Control of wake-up input polarity * TIM1: Watchdog timing control, Watchdog Window (WDW) or Watchdog Timeout (WTO) mode * TIM2: Cyclic Sense and Forced Wake-Up timing selection Control HS periodic activation in Sleep and Stop modes, Forced Wake-Up mode activation, CAN-INT mode selection Enable or Disable of Interrupts CAN wake-up and CAN failure status bits IOR WUR TIM $011 $100 $101 HS overtemperature bit, VSUP, and V2 Low status Wake-up input and real time Lx input state CANL and TXD failure reporting LPC $110 Low Power Control Register (LPC) on page 44 Interrupt Register (INTR) on page 45 CANH and RXD failure reporting INTR $111 Interrupt source 33742 38 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. Mode Control Register (MCR) Tables 10 through 12 describe various Mode Control Register information. Table 10. Mode Control Register MCR $000b Reset Value Reset Condition (Write) (Note 50) R/W W R - - D3 - BATFAIL (Note 49) - - D2 MCTR2 VDDTEMP 0 POR, RESET D1 MCTR1 GFAIL 0 POR, RESET D0 MCTR0 WDRST 0 POR, RESET 0 0 0 0 1 1 1 0 1 Normal Standby Stop, Watchdog OFF (Note 51) Stop, Watchdog ON (Note 51) Sleep (Note 52) Normal Standby Stop Table 11. Mode Control Register Control Bits MCTR2 MCTR 1 0 0 MCTR 0 0 33742 Mode Enter/Exit Debug Mode Description To enter/exit Debug Mode, refer to detailed description in Debug Mode: Hardware and Software Debug with the 33742, page 25. - - - Freescale Semiconductor, Inc... 0 1 1 - Notes 49. BATFAIL bit cannot be set by SPI. BATFAIL is set when VSUP falls below 3.0 V. 50. See Table 8, page 38, for definitions of reset conditions. 1 1 1 1 0 0 1 1 0 1 0 1 - No Watchdog running. Debug Mode. Notes 51. Watchdog ON or OFF depends on RCR bit D3. 52. Before entering Sleep mode, bit BATFAIL in MCR must be previously cleared (MCR read operation), and bit NOSTOP in RCR must be previously set to 1. Table 12. Mode Control Register Status Bits Name BATFAIL Value 0 1 0 VDDTEMP 1 0 GFAIL 1 0 1 Description VSUP was not below VBF. VSUP has been below VBF. No overtemperature pre-warning. Temperature pre-warning on VDD regulator (bit latched). No failure. CAN Failure or HS overtemperature or V2 low. No watchdog reset occurred. Watchdog reset occurred. WDRST ------------------------------------ MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33742 39 Freescale Semiconductor, Inc. Reset Control Register (RCR) Tables 13 and 14 contain various Reset Control Register information. Table 13. Reset Control Register RCR $001b Reset Value Reset Condition (Write) (Note 53) R/W W R - - D3 WDSTOP 1 POR, RESET, STO2NR D2 NOSTOP 0 POR, NR2N, NR2STB D1 CAN SLEEP 0 POR, NR2N, NR2STB D0 RSTTH 0 POR CAN SLEEP NOSTOP Table 14. Reset Control Register Control Bits Name WDSTOP Value 0 1 0 1 0 1 0 1 Description No Watchdog in Stop Mode. Watchdog runs in Stop Mode. Device cannot enter Sleep Mode. Sleep mode allowed. Device can enter Sleep Mode. CAN Sleep Mode disable (despite D0 bit in CAN register). CAN Sleep Mode enabled (in addition to D0 in CAN register). Reset Threshold 1 selected (typ 4.6 V). Reset Threshold 2 selected (typ 4.2 V). Freescale Semiconductor, Inc... Notes 53. See Table 8, page 38, for definitions of reset conditions. RSTTH ------------------------------------ CAN Register (CAN) Tables 15 through 18 contain various CAN register information. Table 15 describes control of the high-speed CAN module, mode, slew rate, and wake-up. Table 15. CAN Register CAN $010b Reset Value Reset Condition (Write) (Note 54) R/W W R - - D3 CANCLR CANWU 0 POR D2 SC1 CAN-F 0 POR D1 SC0 CAN-UF 0 POR D0 MODE THERMCUR 1 NR2N, STB2N Table 16. CANCLR Control Bits Value 0 1 No effect. Re-enables CAN driver after TXD permanent dominant or RXD permanent recessive failure occurred. Failure recovery conditions must occur to re-enable. Description High-Speed CAN Transceiver Modes The MODE bit (D0) controls the state of the CAN interface, TXRX or Sleep mode (Table 17). SC0 bit (D1) defines the slew rate when the CAN module is in TXRX, and it controls the wakeup option (wake-up enable or disable) when the CAN module is in Sleep mode. Table 17. CAN High-Speed Transceiver Modes SC1 0 0 1 SC0 0 1 0 MODE 0 0 0 CAN Mode (Pass 1.1) CAN TXRX, Slew Rate 0 CAN TXRX, Slew Rate 1 CAN TXRX, Slew Rate 2 Notes 54. See Table 8, page 38, for definitions of reset conditions. 33742 40 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. Table 18. CAN Register Status Bits Name CANWU Value 0 1 0 1 0 1 0 THERMCUR 1 Description No CAN wake-up occurred. CAN wake-up occurred. No CAN failure. CAN failure (Note 55). Identified CAN failure (Note 55). Non-identified CAN failure. No overtemperature or overcurrent on CANH or CANL drivers. Overtemperature or overcurrent on CANH or CANL drivers. CAN-F CAN-UF Freescale Semiconductor, Inc... Notes 55. Error bits are latched in the CAN register. ------------------------------------ Input/Output Register (IOR) Tables 19 through 21 contain various Input/Output Register information. Table 20 provides information about HS control in Normal and Standby modes, while Table 21 provides status bit information. Table 19. Input/Output Register IOR $011b Reset Value Reset Condition (Write) (Note 56) R/W W R - - D3 - V2LOW - - D2 HSON HSOT 0 POR D1 - VSUPLOW - - D0 - DEBUG - - V2LOW Value 0 1 Table 20. HSON Control Bits HS State HS OFF, in Normal and Standby modes. HS ON, in Normal and Standby modes (Note 57). Notes 57. When HS is turned OFF due to an overtemperature condition, it can be turned ON again by setting the appropriate control bit to 1. Error bits are latched in the IOR register. Table 21. Input/Output Register Status Bits Name Value 0 1 0 1 0 1 0 DEBUG 1 V2 > 4.0 V. V2 < 4.0 V. No HS overtemperature. HS overtemperature. VSUP > 6.1 V. VSUP < 6.1 V. 33742 not in Debug mode. 33742 accepts command to go to Debug modes (no Watchdog). Description Notes 56. See Table 8, page 38, for definitions of reset conditions. HSOT VSUPLOW ------------------------------------ MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33742 41 Freescale Semiconductor, Inc. Wake-Up Register (WUR) Tables 22 through 24 contain various Wake-Up Register information. Local wake-up inputs L0:L3 can be used in both Normal and Standby modes as port expander, as well as for waking up the 33742 from Sleep or Stop modes (Table 22). Table 22. Wake-Up Register WUR $100b Reset Value Reset Condition (Write) (Note 58) R/W W R - - D3 LCTR3 L3WU 0 D2 LCTR2 L2WU 0 D1 LCTR1 L1WU 0 D0 LCTR0 L0WU 0 x 0 0 1 1 x 0 1 0 1 1 x x x x 1 x x x x - x x 1 0 Table 23. Wake-Up Register Control Bits LCTR3 LCTR2 LCTR1 LCTR0 x x x x 0 0 0 1 L0:L1 Config Inputs Disabled High Level Sensitive Low Level Sensitive Both Level Sensitive Inputs Disabled High Level Sensitive Low Level Sensitive Both Level Sensitive - L2:L3 Config POR, NR2R, N2R, STB2R, STO2R Freescale Semiconductor, Inc... Notes 58. See Table 8, page 38, for definitions of reset conditions. Wake-up inputs can be configured by pair. L0 and L1 can be configured together, and L2 and L3 can be configured together (Table 23). x = Don't care. Table 24. Wake-Up Register Status Bits (Note 59) Name L3WU L2WU L1WU L0WU Value 0 or 1 0 or 1 0 or 1 0 or 1 Description If bit = 1, wake-up occurred from Sleep or Stop modes; if bit = 0, no wake-up has occurred. When device is in Normal or Standby mode, bit reports the State on Lx terminal (LOW or HIGH) (0 = Lx LOW, 1 = Lx HIGH) Notes 59. WUR status bits have two functions. After 33742 wake-up, they indicate the wake up source; for example, L2WU set at 1 if wake-up source is L2 input. After 33742 wake-up and once the WUR register has been read, status bits indicate the realtime state of the Lx inputs (1 = Lx is above threshold, 0 = Lx input is below threshold). If after a wake-up from Lx input a watchdog timeout occurs before the first reading of the WUR register, the LxWU bits are reset. This can occur only if the 33742 was in Stop Mode. ------------------------------------ 33742 42 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. Timing Register (TIM1/2) Tables 25 through 29 contain various Timing Register information. The TIM register is composed of two subregisters: 1. TIM1--Controls the watchdog timing selection as well as either the watchdog window or the watchdog timeout option (Figure 25 and Figure 26, respectively). TIM1 is selected when bit D3 is 0 (Table 25). Watchdog timing characteristics are described in Table 26. 2. TIM2--Selects an appropriate timing for sensing the wake-up circuitry or cyclically supplying devices by switching the HS on or off. TIM2 is selected when bit D3 is 1 (Table 27). Figure 27, page 44, describes HS operation when cyclic sense is selected. Cyclic sense timing characteristics are described in Table 29, page 44. Window Closed No Watchdog Clear Allowed Window Open for Watchdog Clear Watchdog Timing x 50% Watchdog Timing x 50% Watchdog Period (Watchdog Timing Selected by TIM1 Bit WDW =1) Figure 25. Window Watchdog Window Open for Watchdog Clear Freescale Semiconductor, Inc... Both subregisters also report the CANL and TXD diagnostic. Table 25. TIM1 Timing and CANL Failure Diagnostic Register TIM1 $101b Reset Value Reset Condition (Write) (Note 60) R/W W R - - D3 0 D2 WDW D1 WDT1 D0 WDT0 TXPD 0 Watchdog Period (Watchdog Timing Selected by TIM1 Bit WDW = 0) Figure 26. Timeout Watchdog Table 27. Timing Register Status Bits Name CANL2VDD Value 0 1 0 1 0 1 0 1 Failure Description No CANL short to VDD. CANL short to VDD. No CANL short to VSUP . CANL short to VSUP . No CANL short to GND. CANL short to GND. No TXD dominant TXD dominant. CANL2VDD CANL2BAT CANL2GND - - 0 POR, RESET 0 POR, RESET POR, RESET CANL2BAT Notes 60. See Table 8, page 38, for definitions of reset conditions. CANL2GND Table 26. TIM1 Control Bits WDW WDT1 WDT0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Timing (ms typ) 9.75 45 100 350 9.75 45 100 350 Parameter Watchdog Period 1 Watchdog Period 2 Watchdog Period 3 Watchdog Period 4 Watchdog Period 1 Watchdog Period 2 Watchdog Period 3 Watchdog Period 4 Description TXPD Table 28. TIM2 Timing and CANL Failure Diagnostic Register TIM2 No Window Watchdog $101b Reset Value Reset Condition (Write) (Note 61) R/W W R - - D3 1 D2 CSP2 D1 CSP1 D0 CSP0 TXPD 0 POR, RESET CANL2VDD CANL2BAT CANL2GND - - 0 POR, RESET 0 POR, RESET Watchdog Window enabled (Window length is half the Watchdog Timing). Notes 61. See Table 8, page 38, for definitions of reset conditions. MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33742 43 Freescale Semiconductor, Inc. Cyclic Sense Timing, ON Time Table 29. TIM2 Control Bits CSP2 CSP1 CSP0 Cyclic Sense Timing (ms) 4.6 9.25 18.5 37 74 95.5 191 388 Parameter Cyclic Sense/FWU Timing 1 Cyclic Sense/FWU Timing 2 Cyclic Sense/FWU Timing 3 Cyclic Sense/FWU Timing 4 Cyclic Sense/FWU Timing 5 Cyclic Sense/FWU Timing 6 Cyclic Sense/FWU Timing 7 Cyclic Sense/FWU Timing 8 HS ON HS Cyclic Sense Timing, OFF Time HS OFF 0 10 s 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Sample Lx Sampling Point time Figure 27. HS Operation When Cyclic Sense Is Selected Freescale Semiconductor, Inc... ------------------------------------ Low Power Control Register (LPC) Tables 30 through 34 contain various Low Power Control Register information. The LPC register controls: * The state of HS in Stop and Sleep modes (HS permanently OFF or HS cyclic). * Enable or disable of the forced wake-up function (33742 automatic wake-up after time spent in Sleep or Stop modes; time is defined by the TIM2 subregister). * Enable or disable the sense of the wake-up inputs (Lx) at the sampling point of the Cyclic Sense period (LX2HS bit). (Refer to Reset Control Register (RCR) on page 40 for details of the LPC register setup required for proper cyclic sense or direct wake-up operation. The LPC register also reports the CANH and RXD diagnostic. Table 30. Low Power Control Register LPC $110b Reset Value Reset Condition (Write) (Note 62) R/W W D3 LX2HS D2 FWU D1 CAN-INT D0 HSAUTO RXPR 0 Value (Note 63) 0 1 Table 31. LX2HS Control Bits Value 0 1 No. Yes. Lx inputs sensed at sampling point. Wake-Up Inputs Supplied by HS Table 32. HSAUTO Control Bits Value 0 1 Auto-Timing HS in Sleep and Stop Modes OFF. ON, HS Cyclic, period defined in TIM2 subregister. Table 33. CAN-INT Control Bits Description Interrupt as soon as CAN bus failure detected. Interrupt when CAN bus failure detected and fully identified. R CANH2VDD CANH2BAT CANH2GND - - 0 0 0 POR, POR, POR, POR, NR2R, N2R, NR2R, N2R, NR2R, N2R, NR2R, N2R, STB2R, STB2R, STB2R, STB2R, STO2R STO2R STO2R STO2R Notes 62. See Table 8, page 38, for definitions of reset conditions. Notes 63. If CAN-INT is at 0, any undetermined CAN failure will be latched in the CAN register (bit D1: CAN-UF) and can be accessed by SPI (refer to CAN Register (CAN) on page 40). After reading the CAN register or setting CAN-INT to 1, it will be cleared automatically. The existence of CAN-UF always has priority over clearing, meaning that a further undetermined CAN failure does not allow clearing the CAN-UF bit. 33742 44 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. Table 34. LPC Status Bits Name CANH2VDD Value 0 1 0 1 0 1 0 1 Failure Description No CANH short to VDD. CANH short to VDD. No CANH short to VSUP. CANH short to VSUP. No CANH short to GND. CANH short to GND. No RXD permanent recessive. RXD permanent recessive. ------------------------------------ CANH2BAT CANH2GND RXPR Freescale Semiconductor, Inc... Interrupt Register (INTR) Tables 35 through 37 contain various Interrupt Register information. The INTR register allows masking or enabling the interrupt source. A read operation identifies the interrupt source. Table 37 provides status bit information. The status bits of the INTR register content are copies of the IOR, CAN, TIM, and LPC registers status content. To clear the Interrupt Register bits, the IOR, CAN, TIM, and/or LPC registers must be cleared (read register) and the recovery condition must occur. Errors bits are latched in the CAN register and the IOR register. Table 35. Interrupt Register INTR R/W W $111b R Reset Value Reset Condition (Write) (Note 65) - - VSUPLOW 0 POR, RST D3 VSUPLOW D2 HSOTV2LOW (Note 64) HSOT 0 POR, RST D1 VDDTEMP D0 CANF Table 36. Interrupt Register Control Bits Name CANF VDDTEMP HSOT - V2LOW VSUPLOW Description Mask bit for CAN failures. Mask bit for VDD medium temperature (pre-warning). Mask bit for HS overtemperature AND V2 < 4.0 V. Mask bit for VSUP < 6.1 V. VDDTEMP 0 POR, RST CANF 0 POR, RST When the mask bit is set, the INT terminal goes low if the appropriate condition occurs. Upon a wake-up condition from Stop mode due to overcurrent detection (IDDS-WU1 or IDDS-WU2), an INT pulse is generated; however, INTR register content remains at 0000 (not bit set into the INTR register). Table 37. Interrupt Register Status Bits Name VSUPLOW Value 0 1 0 1 0 VDDTEMP 1 0 1 Description No VSUP < 6.1 V. VSUP < 6.1 V. No HS overtemperature. HS overtemperature. No VDD medium temperature (prewarning). VDD medium temperature (prewarning). No CAN failure. CAN failure. Notes 64. If only HSOT - V2LOW interrupt is selected (only bit D2 set in INTR register), reading INTR register bit D2 leads to two possibilities: 1. Bit D2 = 1: Interrupt source is HSOT. 2. Bit D2 = 0: Interrupt source is V2LOW. HSOT and V2LOW bits status are available in the IOR register. 65. See Table 8, page 38, for definitions of reset conditions. HSOT CANF MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33742 45 Freescale Semiconductor, Inc. PACKAGE AND THERMAL CONSIDERATIONS The 33742 is a standard surface mount SOIC 28 package. In order to improve the thermal performances of the SOIC 28 package, eight terminals are internally connected to the lead frame and are used for heat transfer to the printed circuit board. APPLICATIONS Figure 28 shows a typical 33742 application. VPWR R5 D1 Q1 V2 Freescale Semiconductor, Inc... Rp R1 SW1 to L0 C6 C1 VSUP C2 VSUP monitor Dual Voltage Regulator VDD Monitor V2CTRL 5.0 V/200 mA C10 VDD C4 C5 V2 HS L0 HS Control Mode Control Oscillator Interrupt Watchdog Reset V2 C3 INT WDOG RST Rp R2 SW2 to L1 C7 L1 L2 L3 Programmable Wake-Up Input SPI Interface MOSI SCLK MISO CS MCU CANH CANL SW3 R3 Rd C8 to L2 Internal Module Supply 1.0 Mbps CAN Physical Interface V2 TXD RXD GND Safe Circuitry Clamp(1) SW4 R4 C9 to L3 Rd Connector Legend D1: Example: 1N4002 type Q1: MJD32C R1, R2, R3, R4: 10 k Rp, Rd: Example: 1.0 k depending on switch type. R5: 2.2 k C1: 10 F C2: 100 nF C3: 47 F C4: 100 nF C5: 47 F tantalum or 100 F chemical C6, C7, C8, C9, C10: 100 nF (1) Clamp circuit to ensure max ratings for HS (HS from -0.3 V to VSUP + 0.3) are respected. Figure 28. 33742 Typical Application Schematic 33742 46 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. VPWR D1 VSUP C1 C2 V2CTRL VSUP Monitor Dual Voltage Regulator VDD Monitor 5.0 V/200 mA V2 VDD C3 C4 MCU V2 33742 Partial Block Diagram GND Freescale Semiconductor, Inc... Legend D1: Example: 1N4002 type C1: 10 F C2: 100 nF C3: 47 F C4: 100 nF Figure 29. 33742 Application Without External Ballast Transistor on V2 Regulator CANH CANH CH R5 CANL (33742) CL CANL CAN Connector Legend R6, R7: 30 CL, CH: 220 pF CS: > 470 pF CL CS CANH (33742) CH R6 R7 CANH (33742) CANL (33742) CANL CAN Connector Legend R5: 60 CL, CH: 220 pF Figure 30. CAN Bus Standard Termination Figure 31. CAN Bus Split Termination MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33742 47 Freescale Semiconductor, Inc. PACKAGE DIMENSIONS DW SUFFIX 28-LEAD SOICW PLASTIC PACKAGE CASE 751F-05 ISSUE F A D 28 15 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.13 0.29 0.35 0.49 0.23 0.32 17.80 18.05 7.40 7.60 1.27 BSC 10.05 10.55 0.41 0.90 0 8 M E H 1 14 PIN 1 IDENT Freescale Semiconductor, Inc... B 0.25 M B e B 0.025 M A1 0.10 SEATING PLANE L C C CA S DIM A A1 B C D E e H L B S 33742 48 A For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. NOTES Freescale Semiconductor, Inc... MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33742 49 Freescale Semiconductor, Inc. NOTES Freescale Semiconductor, Inc... 33742 50 For More Information On This Product, Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA Freescale Semiconductor, Inc. NOTES Freescale Semiconductor, Inc... MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA For More Information On This Product, Go to: www.freescale.com 33742 51 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their respective owners. (c) Motorola, Inc. 2004 HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573, Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 HOME PAGE: http://motorola.com/semiconductors For More Information On This Product, Go to: www.freescale.com MC33742 |
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